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Searched refs:MASK_ALL_BITS (Results 1 – 10 of 10) sorted by relevance

/external/u-boot/drivers/ddr/marvell/a38x/
Dddr3_training.c146 {0x1034, 0x38000, MASK_ALL_BITS},
147 {0x1038, 0x0, MASK_ALL_BITS},
148 {0x10b0, 0x0, MASK_ALL_BITS},
149 {0x10b8, 0x0, MASK_ALL_BITS},
150 {0x10c0, 0x0, MASK_ALL_BITS},
151 {0x10f0, 0x0, MASK_ALL_BITS},
152 {0x10f4, 0x0, MASK_ALL_BITS},
153 {0x10f8, 0xff, MASK_ALL_BITS},
154 {0x10fc, 0xffff, MASK_ALL_BITS},
155 {0x1130, 0x0, MASK_ALL_BITS},
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Dddr3_training_bist.c45 …ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_BUFFER_SIZE_REG, pattern_addr_length, MASK_ALL_BITS… in ddr3_tip_bist_activate()
55 ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_BUFFER_OFFS_REG, offset, MASK_ALL_BITS); in ddr3_tip_bist_activate()
65 ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_CTRL_REG, 0, MASK_ALL_BITS); in ddr3_tip_bist_activate()
87 MASK_ALL_BITS); in ddr3_tip_bist_read_result()
93 MASK_ALL_BITS); in ddr3_tip_bist_read_result()
100 MASK_ALL_BITS); in ddr3_tip_bist_read_result()
106 MASK_ALL_BITS); in ddr3_tip_bist_read_result()
236 ddr3_tip_if_read(0, ACCESS_TYPE_UNICAST, 0, reg_map[subphy], &read_data, MASK_ALL_BITS); in mv_ddr_tip_bist()
433 ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_CTRL_REG, 0, MASK_ALL_BITS); in mv_ddr_bist_tx()
466 ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_BUFFER_SIZE_REG, pattern_addr_len, MASK_ALL_BITS); in mv_ddr_odpg_bist_prepare()
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Dddr3_training_leveling.c91 MASK_ALL_BITS)); in ddr3_tip_dynamic_read_leveling()
134 MASK_ALL_BITS)); in ddr3_tip_dynamic_read_leveling()
221 ODPG_DATA_CTRL_REG, 0, MASK_ALL_BITS); in ddr3_tip_dynamic_read_leveling()
278 ODPG_DATA_CTRL_REG, 0x0, MASK_ALL_BITS)); in ddr3_tip_dynamic_read_leveling()
287 ODPG_DATA_CTRL_REG, 0x0, MASK_ALL_BITS)); in ddr3_tip_dynamic_read_leveling()
321 MASK_ALL_BITS)); in ddr3_tip_dynamic_read_leveling()
466 MASK_ALL_BITS)); in ddr3_tip_dynamic_per_bit_read_leveling()
509 MASK_ALL_BITS)); in ddr3_tip_dynamic_per_bit_read_leveling()
594 ODPG_DATA_CTRL_REG, 0, MASK_ALL_BITS); in ddr3_tip_dynamic_per_bit_read_leveling()
635 MASK_ALL_BITS)); in ddr3_tip_dynamic_per_bit_read_leveling()
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Dddr3_training_ip_engine.c414 MASK_ALL_BITS)); in ddr3_tip_ip_training()
561 ODPG_DATA_CTRL_REG, 0, MASK_ALL_BITS); in ddr3_tip_ip_training()
586 MASK_ALL_BITS)); in ddr3_tip_load_pattern_to_odpg()
592 MASK_ALL_BITS)); in ddr3_tip_load_pattern_to_odpg()
599 MASK_ALL_BITS)); in ddr3_tip_load_pattern_to_odpg()
605 MASK_ALL_BITS)); in ddr3_tip_load_pattern_to_odpg()
610 MASK_ALL_BITS)); in ddr3_tip_load_pattern_to_odpg()
615 ODPG_DATA_BUFFER_OFFS_REG, load_addr, MASK_ALL_BITS)); in ddr3_tip_load_pattern_to_odpg()
797 MASK_ALL_BITS)); in ddr3_tip_read_training_result()
891 ODPG_DATA_CTRL_REG, reg_data, MASK_ALL_BITS)); in ddr3_tip_load_pattern_to_mem()
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Dmv_ddr_plat.c248 if (mask != MASK_ALL_BITS) { in dunit_write()
249 dunit_read(addr, MASK_ALL_BITS, &reg_val); in dunit_write()
289 dunit_read(ODPG_ENABLE_REG, MASK_ALL_BITS, &data); in mv_ddr_is_odpg_done()
332 dunit_read(DRAM_INIT_CTRL_STATUS_REG, MASK_ALL_BITS, &data); in mv_ddr_is_training_done()
580 dunit_read(PHY_REG_FILE_ACCESS_REG, MASK_ALL_BITS, &reg_val); in is_prfa_done()
600 dunit_write(PHY_REG_FILE_ACCESS_REG, MASK_ALL_BITS, reg_val); in prfa_write()
602 dunit_write(PHY_REG_FILE_ACCESS_REG, MASK_ALL_BITS, reg_val); in prfa_write()
624 dunit_read(PHY_REG_FILE_ACCESS_REG, MASK_ALL_BITS, &reg_val); in prfa_read()
630 dunit_read(PHY_REG_FILE_ACCESS_REG, MASK_ALL_BITS, &reg_val); in prfa_read()
Dddr3_training_pbs.c61 DUAL_DUNIT_CFG_REG, cs_enable_reg_val, MASK_ALL_BITS)); in ddr3_tip_pbs()
72 ddr3_tip_read_adll_value(dev_num, nominal_adll, reg_addr, MASK_ALL_BITS); in ddr3_tip_pbs()
104 res0, MASK_ALL_BITS)); in ddr3_tip_pbs()
223 res0, MASK_ALL_BITS)); in ddr3_tip_pbs()
412 res0, MASK_ALL_BITS)); in ddr3_tip_pbs()
534 res0, MASK_ALL_BITS)); in ddr3_tip_pbs()
637 res0, MASK_ALL_BITS)); in ddr3_tip_pbs()
869 MASK_ALL_BITS)); in ddr3_tip_pbs()
875 ODPG_WR_RD_MODE_ENA_REG, 0xffff, MASK_ALL_BITS)); in ddr3_tip_pbs()
Dddr3_debug.c124 MASK_ALL_BITS)); in ddr3_tip_reg_dump()
564 read_data, MASK_ALL_BITS)); in ddr3_tip_print_stability_log()
569 read_data, MASK_ALL_BITS)); in ddr3_tip_print_stability_log()
574 read_data, MASK_ALL_BITS)); in ddr3_tip_print_stability_log()
606 read_data, MASK_ALL_BITS)); in ddr3_tip_print_stability_log()
1355 reg, MASK_ALL_BITS); in ddr3_tip_run_sweep_test()
1443 ddr3_tip_read_adll_value(dev_num, ctrl_adll, reg, MASK_ALL_BITS); in ddr3_tip_run_sweep_test()
1501 CTX_PHY_REG(cs), MASK_ALL_BITS); in ddr3_tip_run_leveling_sweep_test()
1564 MASK_ALL_BITS)); in ddr3_tip_run_leveling_sweep_test()
1637 ddr3_tip_read_adll_value(dev_num, ctrl_adll, reg, MASK_ALL_BITS); in ddr3_tip_run_leveling_sweep_test()
Dddr3_training_ip_def.h41 #define MASK_ALL_BITS 0xffffffff macro
Dddr3_training_centralization.c84 DUAL_DUNIT_CFG_REG, cs_enable_reg_val, MASK_ALL_BITS)); in ddr3_tip_centralization()
484 MASK_ALL_BITS)); in ddr3_tip_centralization()
522 MASK_ALL_BITS)); in ddr3_tip_special_rx()
Dddr3_training_hw_algo.c58 data_read, MASK_ALL_BITS)); in ddr3_tip_write_additional_odt_setting()