Searched refs:MAX_DELAY (Results 1 – 9 of 9) sorted by relevance
52 #define TST_RETRY_FN_EXP_BACKOFF(FUNC, ERET, MAX_DELAY) \ argument58 if (tst_delay_ < MAX_DELAY * 1000000) { \
521 ui_max_delay = MAX_DELAY; in ddr3_read_leveling_single_cs_rl_mode()943 ui_max_delay = MAX_DELAY; in ddr3_read_leveling_single_cs_window_mode()1133 MAX_DELAY + dram_info->rl_val[cs][idx][DS]; in ddr3_read_leveling_single_cs_window_mode()1135 MAX_DELAY + dram_info->rl_val[cs][idx][DE]; in ddr3_read_leveling_single_cs_window_mode()1138 phase = tmp / MAX_DELAY; in ddr3_read_leveling_single_cs_window_mode()1144 dram_info->rl_val[cs][idx][D] = tmp % MAX_DELAY; in ddr3_read_leveling_single_cs_window_mode()1154 delay_s = dram_info->rl_val[cs][idx][PS] * MAX_DELAY + in ddr3_read_leveling_single_cs_window_mode()1156 delay_e = dram_info->rl_val[cs][idx][PE] * MAX_DELAY + in ddr3_read_leveling_single_cs_window_mode()1160 phase = tmp / MAX_DELAY; in ddr3_read_leveling_single_cs_window_mode()1168 dram_info->rl_val[cs][idx][D] = tmp % MAX_DELAY; in ddr3_read_leveling_single_cs_window_mode()
123 #define MAX_DELAY 0x1F macro
1222 for (delay = 0; delay < MAX_DELAY; delay++) { in ddr3_write_leveling_single_cs()1293 delay = MAX_DELAY; in ddr3_write_leveling_single_cs()
921 u32 adll_val = MAX_DELAY; in ddr3_rx_shift_dqs_to_first_fail()959 MAX_DELAY); in ddr3_rx_shift_dqs_to_first_fail()
916 && (centralization_high_limit[pup] == MAX_DELAY)) in ddr3_center_calc()
160 if (self->far_history_pos >= MAX_DELAY) { in WebRtcAecm_UpdateFarHistory()197 buffer_position += MAX_DELAY; in WebRtcAecm_AlignedFarend()246 MAX_DELAY); in WebRtcAecm_CreateCore()436 memset(aecm->far_history, 0, sizeof(uint16_t) * PART_LEN1 * MAX_DELAY); in WebRtcAecm_InitCore()437 memset(aecm->far_q_domains, 0, sizeof(int) * MAX_DELAY); in WebRtcAecm_InitCore()438 aecm->far_history_pos = MAX_DELAY; in WebRtcAecm_InitCore()
57 uint16_t far_history[PART_LEN1 * MAX_DELAY];59 int far_q_domains[MAX_DELAY];
26 #define MAX_DELAY 100 macro