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Searched refs:MAX_INTERFACE_NUM (Results 1 – 14 of 14) sorted by relevance

/external/u-boot/drivers/ddr/marvell/a38x/
Dddr3_debug.c88 u32 ctrl_sweepres[ADLL_LENGTH][MAX_INTERFACE_NUM][MAX_BUS_NUM];
89 u32 ctrl_adll[MAX_CS_NUM * MAX_INTERFACE_NUM * MAX_BUS_NUM];
90 u32 ctrl_adll1[MAX_CS_NUM * MAX_INTERFACE_NUM * MAX_BUS_NUM];
91 u32 ctrl_level_phase[MAX_CS_NUM * MAX_INTERFACE_NUM * MAX_BUS_NUM];
112 u32 read_data[MAX_INTERFACE_NUM]; in ddr3_tip_reg_dump()
119 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_reg_dump()
133 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_reg_dump()
183 u32 dev_num, enum hws_result result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM]) in hws_ddr3_tip_read_training_result() argument
191 MAX_INTERFACE_NUM); in hws_ddr3_tip_read_training_result()
391 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_print_log()
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Dddr3_training_pbs.c10 u32 nominal_adll[MAX_INTERFACE_NUM * MAX_BUS_NUM];
11 enum hws_training_ip_stat train_status[MAX_INTERFACE_NUM];
12 u8 result_mat[MAX_INTERFACE_NUM][MAX_BUS_NUM][BUS_WIDTH_IN_BITS];
13 u8 result_mat_rx_dqs[MAX_INTERFACE_NUM][MAX_BUS_NUM][MAX_CS_NUM];
15 u8 result_all_bit[MAX_BUS_NUM * BUS_WIDTH_IN_BITS * MAX_INTERFACE_NUM];
16 u8 max_pbs_per_pup[MAX_INTERFACE_NUM][MAX_BUS_NUM];
17 u8 min_pbs_per_pup[MAX_INTERFACE_NUM][MAX_BUS_NUM];
18 u8 max_adll_per_pup[MAX_INTERFACE_NUM][MAX_BUS_NUM];
19 u8 min_adll_per_pup[MAX_INTERFACE_NUM][MAX_BUS_NUM];
20 u32 pbsdelay_per_pup[NUM_OF_PBS_MODES][MAX_INTERFACE_NUM][MAX_BUS_NUM][MAX_CS_NUM];
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Dddr3_training_leveling.c17 static struct write_supp_result wr_supp_res[MAX_INTERFACE_NUM][MAX_BUS_NUM];
68 u32 cs_enable_reg_val[MAX_INTERFACE_NUM] = { 0 }; in ddr3_tip_dynamic_read_leveling()
70 u32 data_read[MAX_INTERFACE_NUM + 1] = { 0 }; in ddr3_tip_dynamic_read_leveling()
71 u8 rl_values[NUM_OF_CS][MAX_BUS_NUM][MAX_INTERFACE_NUM]; in ddr3_tip_dynamic_read_leveling()
79 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) in ddr3_tip_dynamic_read_leveling()
83 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()
142 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()
224 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()
292 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()
315 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()
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Dddr3_training_ip.h14 #define MAX_TOTAL_BUS_NUM (MAX_INTERFACE_NUM * MAX_BUS_NUM)
127 u32 reg_mr0[MAX_INTERFACE_NUM];
128 u32 reg_mr1[MAX_INTERFACE_NUM];
129 u32 reg_mr2[MAX_INTERFACE_NUM];
130 u32 reg_m_r3[MAX_INTERFACE_NUM];
138 u32 read_data_sample[MAX_INTERFACE_NUM];
146 u32 read_data_ready[MAX_INTERFACE_NUM];
178 enum hws_result result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM]);
Dddr3_training_hw_algo.c17 u8 current_vref[MAX_BUS_NUM][MAX_INTERFACE_NUM];
18 u8 last_vref[MAX_BUS_NUM][MAX_INTERFACE_NUM];
19 u16 current_valid_window[MAX_BUS_NUM][MAX_INTERFACE_NUM];
20 u16 last_valid_window[MAX_BUS_NUM][MAX_INTERFACE_NUM];
21 u8 lim_vref[MAX_BUS_NUM][MAX_INTERFACE_NUM];
22 u8 interface_state[MAX_INTERFACE_NUM];
23 u8 vref_window_size[MAX_INTERFACE_NUM][MAX_BUS_NUM];
26 static u8 pup_st[MAX_BUS_NUM][MAX_INTERFACE_NUM];
45 u32 data_read[MAX_INTERFACE_NUM] = { 0 }; in ddr3_tip_write_additional_odt_setting()
180 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in ddr3_tip_vref()
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Dddr3_training_centralization.c20 u32 start_if = 0, end_if = (MAX_INTERFACE_NUM - 1);
21 u8 bus_end_window[NUM_OF_CENTRAL_TYPES][MAX_INTERFACE_NUM][MAX_BUS_NUM];
22 u8 bus_start_window[NUM_OF_CENTRAL_TYPES][MAX_INTERFACE_NUM][MAX_BUS_NUM];
23 u8 centralization_state[MAX_INTERFACE_NUM][MAX_BUS_NUM];
54 enum hws_training_ip_stat training_result[MAX_INTERFACE_NUM]; in ddr3_tip_centralization()
58 u8 centralization_result[MAX_INTERFACE_NUM][BUS_WIDTH_IN_BITS]; in ddr3_tip_centralization()
62 u8 final_pup_window[MAX_INTERFACE_NUM][BUS_WIDTH_IN_BITS]; in ddr3_tip_centralization()
72 u32 cs_enable_reg_val[MAX_INTERFACE_NUM]; in ddr3_tip_centralization()
79 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_centralization()
102 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_centralization()
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Dddr3_init.h95 extern enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
128 extern u8 vref_window_size[MAX_INTERFACE_NUM][MAX_BUS_NUM];
168 int print_adll(u32 dev_num, u32 adll[MAX_INTERFACE_NUM * MAX_BUS_NUM]);
169 int print_ph(u32 dev_num, u32 adll[MAX_INTERFACE_NUM * MAX_BUS_NUM]);
170 int read_phase_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
172 int write_leveling_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
173 u32 pup_ph_values[MAX_INTERFACE_NUM * MAX_BUS_NUM], int reg_addr);
Dddr3_training_ip_engine.c14 u32 phy_reg_bk[MAX_INTERFACE_NUM][MAX_BUS_NUM][BUS_WIDTH_IN_BITS];
16 u32 training_res[MAX_INTERFACE_NUM * MAX_BUS_NUM * BUS_WIDTH_IN_BITS *
18 u8 byte_status[MAX_INTERFACE_NUM][MAX_BUS_NUM]; /* holds the bit status in the byte in wrapper func…
319 [MAX_INTERFACE_NUM * MAX_BUS_NUM * BUS_WIDTH_IN_BITS * search + in ddr3_tip_get_buf_ptr()
362 if (interface_num >= MAX_INTERFACE_NUM) { in ddr3_tip_ip_training()
704 u32 read_data[MAX_INTERFACE_NUM]; in ddr3_tip_read_training_result()
736 if (if_id >= MAX_INTERFACE_NUM) { in ddr3_tip_read_training_result()
850 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_load_all_pattern_to_mem()
855 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_load_all_pattern_to_mem()
907 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in ddr3_tip_load_pattern_to_mem()
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Dddr3_training.c37 enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
364 u32 data_read[MAX_INTERFACE_NUM]; in hws_ddr3_tip_init_controller()
380 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in hws_ddr3_tip_init_controller()
665 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in hws_ddr3_tip_init_controller()
1079 u32 read_data[MAX_INTERFACE_NUM]; in ddr3_tip_if_polling()
1086 end_if = MAX_INTERFACE_NUM - 1; in ddr3_tip_if_polling()
1160 end_if = MAX_INTERFACE_NUM - 1; in ddr3_tip_bus_read_modify_write()
1272 u32 cs_mask[MAX_INTERFACE_NUM]; in ddr3_tip_freq_set()
1286 end_if = MAX_INTERFACE_NUM - 1; in ddr3_tip_freq_set()
1294 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_freq_set()
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Dddr3_training_ip_flow.h183 u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
186 u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
189 u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
Dddr3_training_bist.c77 u32 read_data[MAX_INTERFACE_NUM]; in ddr3_tip_bist_read_result()
126 for (i = 0; i < MAX_INTERFACE_NUM; i++) { in hws_ddr3_run_bist()
185 struct bist_result st_bist_result[MAX_INTERFACE_NUM]; in ddr3_tip_print_bist_res()
189 for (i = 0; i < MAX_INTERFACE_NUM; i++) { in ddr3_tip_print_bist_res()
205 for (i = 0; i < MAX_INTERFACE_NUM; i++) { in ddr3_tip_print_bist_res()
Dddr_topology_def.h80 struct if_params interface_params[MAX_INTERFACE_NUM];
Dmv_ddr_plat.h9 #define MAX_INTERFACE_NUM 1 macro
Dmv_ddr_plat.c1412 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_configure_phy()