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Searched refs:MAX_PUP_NUM (Results 1 – 5 of 5) sorted by relevance

/external/u-boot/drivers/ddr/marvell/axp/
Dddr3_pbs.c42 static u32 skew_array[(MAX_PUP_NUM) * DQ_NUM] = { 0 };
45 extern u32 pbs_locked_dq[MAX_PUP_NUM][DQ_NUM];
46 extern u32 pbs_locked_dm[MAX_PUP_NUM];
47 extern u32 pbs_locked_value[MAX_PUP_NUM][DQ_NUM];
83 u32 skew_sum_array[MAX_PUP_NUM][DQ_NUM] = { {0} }; in ddr3_pbs_tx()
89 u32 pattern_skew_array[MAX_PUP_NUM][DQ_NUM] = { {0} }; in ddr3_pbs_tx()
412 u32 dqs_dly_set[MAX_PUP_NUM] = { 0 }; in ddr3_tx_shift_dqs_adll_step_before_fail()
525 u32 skew_sum_array[MAX_PUP_NUM][DQ_NUM] = { {0} }; in ddr3_pbs_rx()
531 u32 pattern_skew_array[MAX_PUP_NUM][DQ_NUM] = { {0} }; in ddr3_pbs_rx()
1154 u32 first_fail[MAX_PUP_NUM] = { 0 }; /* count first fail per pup */ in ddr3_pbs_per_bit()
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Dddr3_dqs.c63 static int centralization_low_limit[MAX_PUP_NUM] = { 0 };
65 static int centralization_high_limit[MAX_PUP_NUM] = { 0 };
82 extern int per_bit_data[MAX_PUP_NUM][DQ_NUM];
87 extern int per_bit_data[MAX_PUP_NUM][DQ_NUM];
314 u8 analog_pbs[DQ_NUM][MAX_PUP_NUM][DQ_NUM][2]; in ddr3_find_adll_limits()
315 u8 analog_pbs_sum[MAX_PUP_NUM][DQ_NUM][2]; in ddr3_find_adll_limits()
316 int pup_adll_limit_state[MAX_PUP_NUM]; /* hold state of each pup */ in ddr3_find_adll_limits()
964 u32 special_res[MAX_PUP_NUM]; /* hold tmp results */ in ddr3_special_pattern_i_search()
1125 u32 special_res[MAX_PUP_NUM]; /* hold tmp results */ in ddr3_special_pattern_ii_search()
Dddr3_hw_training.h134 #define MAX_PUP_NUM 9 macro
259 u32 wl_val[MAX_CS][MAX_PUP_NUM][7];
260 u32 rl_val[MAX_CS][MAX_PUP_NUM][7];
Dddr3_sdram.c28 u32 pbs_locked_dq[MAX_PUP_NUM][DQ_NUM] = { { 0 } };
29 u32 pbs_locked_dm[MAX_PUP_NUM] = { 0 };
30 u32 pbs_locked_value[MAX_PUP_NUM][DQ_NUM] = { { 0 } };
32 int per_bit_data[MAX_PUP_NUM][DQ_NUM];
Dddr3_write_leveling.c718 memset(dram_info->wl_val, 0, sizeof(u32) * MAX_CS * MAX_PUP_NUM * 7); in ddr3_write_leveling_sw()
1132 u32 flag[MAX_PUP_NUM] = { 0 }; in ddr3_write_leveling_single_cs()