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1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * mcf5271.h -- Definitions for Motorola Coldfire 5271
4  *
5  * (C) Copyright 2006, Lab X Technologies <zachary.landau@labxtechnologies.com>
6  * Based on mcf5272sim.h of uCLinux distribution:
7  *      (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
8  *      (C) Copyright 2000, Lineo Inc. (www.lineo.com)
9  */
10 
11 #ifndef	_MCF5271_H_
12 #define	_MCF5271_H_
13 
14 #define mbar_readLong(x)	*((volatile unsigned long *) (CONFIG_SYS_MBAR + x))
15 #define mbar_readShort(x)	*((volatile unsigned short *) (CONFIG_SYS_MBAR + x))
16 #define mbar_readByte(x)	*((volatile unsigned char *) (CONFIG_SYS_MBAR + x))
17 #define mbar_writeLong(x,y)	*((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) = y
18 #define mbar_writeShort(x,y)	*((volatile unsigned short *) (CONFIG_SYS_MBAR + x)) = y
19 #define mbar_writeByte(x,y)	*((volatile unsigned char *) (CONFIG_SYS_MBAR + x)) = y
20 
21 #define MCF_FMPLL_SYNCR				0x120000
22 #define MCF_FMPLL_SYNSR				0x120004
23 
24 #define MCF_FMPLL_SYNCR_MFD(x)			((x&0x7)<<24)
25 #define MCF_SYNCR_MFD_4X		0x00000000
26 #define MCF_SYNCR_MFD_6X		0x01000000
27 #define MCF_SYNCR_MFD_8X		0x02000000
28 #define MCF_SYNCR_MFD_10X		0x03000000
29 #define MCF_SYNCR_MFD_12X		0x04000000
30 #define MCF_SYNCR_MFD_14X		0x05000000
31 #define MCF_SYNCR_MFD_16X		0x06000000
32 #define MCF_SYNCR_MFD_18X		0x07000000
33 
34 #define MCF_FMPLL_SYNCR_RFD(x)			((x&0x7)<<19)
35 #define MCF_SYNCR_RFD_DIV1		0x00000000
36 #define MCF_SYNCR_RFD_DIV2		0x00080000
37 #define MCF_SYNCR_RFD_DIV4		0x00100000
38 #define MCF_SYNCR_RFD_DIV8		0x00180000
39 #define MCF_SYNCR_RFD_DIV16		0x00200000
40 #define MCF_SYNCR_RFD_DIV32		0x00280000
41 #define MCF_SYNCR_RFD_DIV64		0x00300000
42 #define MCF_SYNCR_RFD_DIV128		0x00380000
43 
44 #define MCF_FMPLL_SYNSR_LOCK			0x8
45 
46 #define MCF_WTM_WCR				0x140000
47 #define MCF_WTM_WCNTR				0x140004
48 #define MCF_WTM_WSR				0x140006
49 #define MCF_WTM_WCR_EN				0x0001
50 
51 #define MCF_RCM_RCR				0x110000
52 #define MCF_RCM_RCR_FRCRSTOUT			0x40
53 #define MCF_RCM_RCR_SOFTRST			0x80
54 
55 #define MCF_GPIO_PODR_ADDR			0x100000
56 #define MCF_GPIO_PODR_DATAH			0x100001
57 #define MCF_GPIO_PODR_DATAL			0x100002
58 #define MCF_GPIO_PODR_BUSCTL			0x100003
59 #define MCF_GPIO_PODR_BS			0x100004
60 #define MCF_GPIO_PODR_CS			0x100005
61 #define MCF_GPIO_PODR_SDRAM			0x100006
62 #define MCF_GPIO_PODR_FECI2C			0x100007
63 #define MCF_GPIO_PODR_UARTH			0x100008
64 #define MCF_GPIO_PODR_UARTL			0x100009
65 #define MCF_GPIO_PODR_QSPI			0x10000A
66 #define MCF_GPIO_PODR_TIMER			0x10000B
67 
68 #define MCF_GPIO_PDDR_ADDR			0x100010
69 #define MCF_GPIO_PDDR_DATAH			0x100011
70 #define MCF_GPIO_PDDR_DATAL			0x100012
71 #define MCF_GPIO_PDDR_BUSCTL			0x100013
72 #define MCF_GPIO_PDDR_BS			0x100014
73 #define MCF_GPIO_PDDR_CS			0x100015
74 #define MCF_GPIO_PDDR_SDRAM			0x100016
75 #define MCF_GPIO_PDDR_FECI2C			0x100017
76 #define MCF_GPIO_PDDR_UARTH			0x100018
77 #define MCF_GPIO_PDDR_UARTL			0x100019
78 #define MCF_GPIO_PDDR_QSPI			0x10001A
79 #define MCF_GPIO_PDDR_TIMER			0x10001B
80 
81 #define MCF_GPIO_PPDSDR_ADDR			0x100020
82 #define MCF_GPIO_PPDSDR_DATAH			0x100021
83 #define MCF_GPIO_PPDSDR_DATAL			0x100022
84 #define MCF_GPIO_PPDSDR_BUSCTL			0x100023
85 #define MCF_GPIO_PPDSDR_BS			0x100024
86 #define MCF_GPIO_PPDSDR_CS			0x100025
87 #define MCF_GPIO_PPDSDR_SDRAM			0x100026
88 #define MCF_GPIO_PPDSDR_FECI2C			0x100027
89 #define MCF_GPIO_PPDSDR_UARTH			0x100028
90 #define MCF_GPIO_PPDSDR_UARTL			0x100029
91 #define MCF_GPIO_PPDSDR_QSPI			0x10002A
92 #define MCF_GPIO_PPDSDR_TIMER			0x10002B
93 
94 #define MCF_GPIO_PCLRR_ADDR			0x100030
95 #define MCF_GPIO_PCLRR_DATAH			0x100031
96 #define MCF_GPIO_PCLRR_DATAL			0x100032
97 #define MCF_GPIO_PCLRR_BUSCTL			0x100033
98 #define MCF_GPIO_PCLRR_BS			0x100034
99 #define MCF_GPIO_PCLRR_CS			0x100035
100 #define MCF_GPIO_PCLRR_SDRAM			0x100036
101 #define MCF_GPIO_PCLRR_FECI2C			0x100037
102 #define MCF_GPIO_PCLRR_UARTH			0x100038
103 #define MCF_GPIO_PCLRR_UARTL			0x100039
104 #define MCF_GPIO_PCLRR_QSPI			0x10003A
105 #define MCF_GPIO_PCLRR_TIMER			0x10003B
106 
107 #define MCF_GPIO_PAR_AD				0x100040
108 #define MCF_GPIO_PAR_BUSCTL			0x100042
109 #define MCF_GPIO_PAR_BS				0x100044
110 #define MCF_GPIO_PAR_CS				0x100045
111 #define MCF_GPIO_PAR_SDRAM			0x100046
112 #define MCF_GPIO_PAR_FECI2C			0x100047
113 #define MCF_GPIO_PAR_UART			0x100048
114 #define MCF_GPIO_PAR_QSPI			0x10004A
115 #define MCF_GPIO_PAR_TIMER			0x10004C
116 
117 #define MCF_DSCR_EIM				0x100050
118 #define MCF_DCSR_FEC12C 			0x100052
119 #define MCF_DCSR_UART				0x100053
120 #define MCF_DCSR_QSPI				0x100054
121 #define MCF_DCSR_TIMER				0x100055
122 
123 #define MCF_CCM_CIR				0x11000A
124 #define MCF_CCM_CIR_PRN_MASK			0x3F
125 #define MCF_CCM_CIR_PIN_LEN			6
126 #define MCF_CCM_CIR_PIN_MCF5270			0x002e
127 #define MCF_CCM_CIR_PIN_MCF5271			0x0032
128 
129 #define MCF_GPIO_AD_ADDR23			0x80
130 #define MCF_GPIO_AD_ADDR22			0x40
131 #define MCF_GPIO_AD_ADDR21			0x20
132 #define MCF_GPIO_AD_DATAL			0x01
133 #define MCF_GPIO_AD_MASK			0xe1
134 
135 #define MCF_GPIO_PAR_CS_PAR_CS2			0x04
136 
137 #define MCF_GPIO_SDRAM_CSSDCS_00		0x00	/* CS[3:2] pins: CS3, CS2 */
138 #define MCF_GPIO_SDRAM_CSSDCS_01		0x40	/* CS[3:2] pins: CS3, SD_CS0 */
139 #define MCF_GPIO_SDRAM_CSSDCS_10		0x80	/* CS[3:2] pins: SD_CS1, SC2 */
140 #define MCF_GPIO_SDRAM_CSSDCS_11		0xc0	/* CS[3:2] pins: SD_CS1, SD_CS0 */
141 #define MCF_GPIO_SDRAM_SDWE			0x20	/* WE pin */
142 #define MCF_GPIO_SDRAM_SCAS			0x10	/* CAS pin */
143 #define MCF_GPIO_SDRAM_SRAS			0x08	/* RAS pin */
144 #define MCF_GPIO_SDRAM_SCKE			0x04	/* CKE pin */
145 #define MCF_GPIO_SDRAM_SDCS_00			0x00	/* SD_CS[0:1] pins: GPIO, GPIO */
146 #define MCF_GPIO_SDRAM_SDCS_01			0x01	/* SD_CS[0:1] pins: GPIO, SD_CS0 */
147 #define MCF_GPIO_SDRAM_SDCS_10			0x02	/* SD_CS[0:1] pins: SD_CS1, GPIO */
148 #define MCF_GPIO_SDRAM_SDCS_11			0x03	/* SD_CS[0:1] pins: SD_CS1, SD_CS0 */
149 
150 #define MCF_GPIO_PAR_UART_U0RTS			0x0001
151 #define MCF_GPIO_PAR_UART_U0CTS			0x0002
152 #define MCF_GPIO_PAR_UART_U0TXD			0x0004
153 #define MCF_GPIO_PAR_UART_U0RXD			0x0008
154 #define MCF_GPIO_PAR_UART_U1RXD_UART1		0x0C00
155 #define MCF_GPIO_PAR_UART_U1TXD_UART1		0x0300
156 
157 /* Bit definitions and macros for PAR_QSPI */
158 #define MCF_GPIO_PAR_QSPI_PCS1_UNMASK		0x3F
159 #define MCF_GPIO_PAR_QSPI_PCS1_PCS1		0xC0
160 #define MCF_GPIO_PAR_QSPI_PCS1_SDRAM_SCKE	0x80
161 #define MCF_GPIO_PAR_QSPI_PCS1_GPIO		0x00
162 #define MCF_GPIO_PAR_QSPI_PCS0_UNMASK		0xDF
163 #define MCF_GPIO_PAR_QSPI_PCS0_PCS0		0x20
164 #define MCF_GPIO_PAR_QSPI_PCS0_GPIO		0x00
165 #define MCF_GPIO_PAR_QSPI_SIN_UNMASK		0xE7
166 #define MCF_GPIO_PAR_QSPI_SIN_SIN		0x18
167 #define MCF_GPIO_PAR_QSPI_SIN_I2C_SDA		0x10
168 #define MCF_GPIO_PAR_QSPI_SIN_GPIO		0x00
169 #define MCF_GPIO_PAR_QSPI_SOUT_UNMASK		0xFB
170 #define MCF_GPIO_PAR_QSPI_SOUT_SOUT		0x04
171 #define MCF_GPIO_PAR_QSPI_SOUT_GPIO		0x00
172 #define MCF_GPIO_PAR_QSPI_SCK_UNMASK		0xFC
173 #define MCF_GPIO_PAR_QSPI_SCK_SCK		0x03
174 #define MCF_GPIO_PAR_QSPI_SCK_I2C_SCL		0x02
175 #define MCF_GPIO_PAR_QSPI_SCK_GPIO		0x00
176 
177 /* Bit definitions and macros for PAR_TIMER for QSPI */
178 #define MCF_GPIO_PAR_TIMER_T3IN_UNMASK		0x3FFF
179 #define MCF_GPIO_PAR_TIMER_T3IN_QSPI_PCS2	0x4000
180 #define MCF_GPIO_PAR_TIMER_T3OUT_UNMASK		0xFF3F
181 #define MCF_GPIO_PAR_TIMER_T3OUT_QSPI_PCS3	0x0040
182 
183 #define MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(x)	(((x)&0x03)<<6)
184 
185 #define MCF_SDRAMC_DCR				0x000040
186 #define MCF_SDRAMC_DACR0			0x000048
187 #define MCF_SDRAMC_DMR0				0x00004C
188 
189 #define MCF_SDRAMC_DCR_RC(x)			(((x)&0x01FF)<<0)
190 #define MCF_SDRAMC_DCR_RTIM(x)			(((x)&0x0003)<<9)
191 #define MCF_SDRAMC_DCR_IS			0x0800
192 #define MCF_SDRAMC_DCR_COC			0x1000
193 #define MCF_SDRAMC_DCR_NAM			0x2000
194 
195 #define MCF_SDRAMC_DACRn_IP			0x00000008
196 #define MCF_SDRAMC_DACRn_PS(x)			(((x)&0x00000003)<<4)
197 #define MCF_SDRAMC_DACRn_MRS			0x00000040
198 #define MCF_SDRAMC_DACRn_CBM(x)			(((x)&0x00000007)<<8)
199 #define MCF_SDRAMC_DACRn_CASL(x)		(((x)&0x00000003)<<12)
200 #define MCF_SDRAMC_DACRn_RE			0x00008000
201 #define MCF_SDRAMC_DACRn_BA(x)			(((x)&0x00003FFF)<<18)
202 
203 #define MCF_SDRAMC_DMRn_BAM_8M			0x007C0000
204 #define MCF_SDRAMC_DMRn_BAM_16M			0x00FC0000
205 #define MCF_SDRAMC_DMRn_V			0x00000001
206 
207 #define MCFSIM_ICR1				0x000C41
208 
209 /* Interrupt Controller (INTC) */
210 #define INT0_LO_RSVD0			(0)
211 #define INT0_LO_EPORT1			(1)
212 #define INT0_LO_EPORT2			(2)
213 #define INT0_LO_EPORT3			(3)
214 #define INT0_LO_EPORT4			(4)
215 #define INT0_LO_EPORT5			(5)
216 #define INT0_LO_EPORT6			(6)
217 #define INT0_LO_EPORT7			(7)
218 #define INT0_LO_SCM			(8)
219 #define INT0_LO_DMA0			(9)
220 #define INT0_LO_DMA1			(10)
221 #define INT0_LO_DMA2			(11)
222 #define INT0_LO_DMA3			(12)
223 #define INT0_LO_UART0			(13)
224 #define INT0_LO_UART1			(14)
225 #define INT0_LO_UART2			(15)
226 #define INT0_LO_RSVD1			(16)
227 #define INT0_LO_I2C			(17)
228 #define INT0_LO_QSPI			(18)
229 #define INT0_LO_DTMR0			(19)
230 #define INT0_LO_DTMR1			(20)
231 #define INT0_LO_DTMR2			(21)
232 #define INT0_LO_DTMR3			(22)
233 #define INT0_LO_FEC_TXF			(23)
234 #define INT0_LO_FEC_TXB			(24)
235 #define INT0_LO_FEC_UN			(25)
236 #define INT0_LO_FEC_RL			(26)
237 #define INT0_LO_FEC_RXF			(27)
238 #define INT0_LO_FEC_RXB			(28)
239 #define INT0_LO_FEC_MII			(29)
240 #define INT0_LO_FEC_LC			(30)
241 #define INT0_LO_FEC_HBERR		(31)
242 #define INT0_HI_FEC_GRA			(32)
243 #define INT0_HI_FEC_EBERR		(33)
244 #define INT0_HI_FEC_BABT		(34)
245 #define INT0_HI_FEC_BABR		(35)
246 #define INT0_HI_PIT0			(36)
247 #define INT0_HI_PIT1			(37)
248 #define INT0_HI_PIT2			(38)
249 #define INT0_HI_PIT3			(39)
250 #define INT0_HI_RNG			(40)
251 #define INT0_HI_SKHA			(41)
252 #define INT0_HI_MDHA			(42)
253 #define INT0_HI_CAN1_BUF0I		(43)
254 #define INT0_HI_CAN1_BUF1I		(44)
255 #define INT0_HI_CAN1_BUF2I		(45)
256 #define INT0_HI_CAN1_BUF3I		(46)
257 #define INT0_HI_CAN1_BUF4I		(47)
258 #define INT0_HI_CAN1_BUF5I		(48)
259 #define INT0_HI_CAN1_BUF6I		(49)
260 #define INT0_HI_CAN1_BUF7I		(50)
261 #define INT0_HI_CAN1_BUF8I		(51)
262 #define INT0_HI_CAN1_BUF9I		(52)
263 #define INT0_HI_CAN1_BUF10I		(53)
264 #define INT0_HI_CAN1_BUF11I		(54)
265 #define INT0_HI_CAN1_BUF12I		(55)
266 #define INT0_HI_CAN1_BUF13I		(56)
267 #define INT0_HI_CAN1_BUF14I		(57)
268 #define INT0_HI_CAN1_BUF15I		(58)
269 #define INT0_HI_CAN1_ERRINT		(59)
270 #define INT0_HI_CAN1_BOFFINT		(60)
271 /* 60-63 Reserved */
272 
273 #endif				/* _MCF5271_H_ */
274