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Searched refs:MCInst_getOpcode (Results 1 – 25 of 26) sorted by relevance

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/external/capstone/arch/ARM/
DARMDisassembler.c415 if (MCInst_getOpcode(Inst) == ARM_tBcc && Val == 0xE) in DecodePredicateOperand()
557 MCOperandInfo *OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo; in AddThumb1SBit()
558 unsigned short NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands; in AddThumb1SBit()
588 switch (MCInst_getOpcode(MI)) { in AddThumbPredicate()
628 OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo; in AddThumbPredicate()
629 NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands; in AddThumbPredicate()
668 OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo; in UpdateThumbVFPPredicate()
669 NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands; in UpdateThumbVFPPredicate()
736 if (MCInst_getOpcode(MI) == ARM_t2IT && ITStatus_instrInITBlock(&(ud->ITBlock))) in _Thumb_getInstruction()
743 if (MCInst_getOpcode(MI) == ARM_t2IT) { in _Thumb_getInstruction()
[all …]
DARMInstPrinter.c408 unsigned Opcode = MCInst_getOpcode(MI), tmp, i, pubOpcode; in ARM_printInst()
721 unsigned int opc = MCInst_getOpcode(MI); in printOperand()
1481 unsigned Opcode = MCInst_getOpcode(MI); in printMSRMaskOperand()
DARMGenAsmWriter.inc6051 uint64_t Bits1 = OpInfo[MCInst_getOpcode(MI)];
6052 uint64_t Bits2 = OpInfo2[MCInst_getOpcode(MI)];
8699 switch (MCInst_getOpcode(MI)) {
/external/capstone/arch/PowerPC/
DPPCInstPrinter.c87 if (MCInst_getOpcode(MI) == PPC_RLWINM) { in PPC_printInst()
127 if ((MCInst_getOpcode(MI) == PPC_OR || MCInst_getOpcode(MI) == PPC_OR8) && in PPC_printInst()
137 if (MCInst_getOpcode(MI) == PPC_RLDICR) { in PPC_printInst()
156 if ((MCInst_getOpcode(MI) == PPC_gBC)||(MCInst_getOpcode(MI) == PPC_gBCA)|| in PPC_printInst()
157 (MCInst_getOpcode(MI) == PPC_gBCL)||(MCInst_getOpcode(MI) == PPC_gBCLA)) { in PPC_printInst()
163 if (isBOCTRBranch(MCInst_getOpcode(MI))) { in PPC_printInst()
172 if ((MCInst_getOpcode(MI) == PPC_B)||(MCInst_getOpcode(MI) == PPC_BA)|| in PPC_printInst()
173 (MCInst_getOpcode(MI) == PPC_BL)||(MCInst_getOpcode(MI) == PPC_BLA)) { in PPC_printInst()
538 if (!PPC_abs_branch(MI->csh, MCInst_getOpcode(MI))) { in printAbsBranchOperand()
753 switch (MCInst_getOpcode(MI)) { in printAliasInstrEx()
DPPCDisassembler.c267 switch (MCInst_getOpcode(Inst)) { in decodeMemRIOperands()
303 if (MCInst_getOpcode(Inst) == PPC_LDU) in decodeMemRIXOperands()
306 else if (MCInst_getOpcode(Inst) == PPC_STDU) in decodeMemRIXOperands()
DPPCGenAsmWriter.inc3592 uint64_t Bits1 = OpInfo[MCInst_getOpcode(MI)];
3593 uint64_t Bits2 = OpInfo2[MCInst_getOpcode(MI)];
4293 switch (MCInst_getOpcode(MI)) {
/external/capstone/arch/X86/
DX86Disassembler.c171 uint32_t Opcode = MCInst_getOpcode(mcInst); in translateImmediate()
221 switch (MCInst_getOpcode(mcInst)) { in translateImmediate()
244 switch (MCInst_getOpcode(mcInst)) { in translateImmediate()
396 Opcode = MCInst_getOpcode(mcInst); in translateRMMemory()
697 if (MCInst_getOpcode(mcInst) == X86_REP_PREFIX) in translateInstruction()
699 else if (MCInst_getOpcode(mcInst) == X86_REPNE_PREFIX) in translateInstruction()
DX86ATTInstPrinter.c516 switch(MCInst_getOpcode(MI)) { in printOperand()
789 if (MI->csh->mode == CS_MODE_64 && MCInst_getOpcode(MI) == X86_CALLpcrel32) { in X86_ATT_printInst()
828 switch(MCInst_getOpcode(MI)) { in X86_ATT_printInst()
907 reg = X86_insn_reg_att(MCInst_getOpcode(MI)); in X86_ATT_printInst()
917 if (X86_insn_reg_att2(MCInst_getOpcode(MI), &reg, &reg2)) { in X86_ATT_printInst()
DX86IntelInstPrinter.c508 reg = X86_insn_reg_intel(MCInst_getOpcode(MI)); in X86_Intel_printInst()
522 if (X86_insn_reg_intel2(MCInst_getOpcode(MI), &reg, &reg2)) { in X86_Intel_printInst()
613 switch(MCInst_getOpcode(MI)) { in printOperand()
DX86GenAsmWriter1_reduce.inc2114 uint32_t Bits = OpInfo[MCInst_getOpcode(MI)];
2777 switch (MCInst_getOpcode(MI)) {
DX86GenAsmWriter_reduce.inc2371 uint32_t Bits = OpInfo[MCInst_getOpcode(MI)];
3091 switch (MCInst_getOpcode(MI)) {
DX86Mapping.c47791 opcode = MCInst_getOpcode(MI); in X86_lockrep()
47825 opcode = MCInst_getOpcode(MI); in X86_lockrep()
DX86GenAsmWriter.inc14166 unsigned int opcode = MCInst_getOpcode(MI);
15658 switch (MCInst_getOpcode(MI)) {
/external/capstone/arch/AArch64/
DAArch64Disassembler.c850 switch (MCInst_getOpcode(Inst)) { in DecodeThreeAddrSRegInstruction()
913 switch (MCInst_getOpcode(Inst)) { in DecodeMoveImmInstruction()
930 if (MCInst_getOpcode(Inst) == AArch64_MOVKWi || in DecodeMoveImmInstruction()
931 MCInst_getOpcode(Inst) == AArch64_MOVKXi) in DecodeMoveImmInstruction()
947 switch (MCInst_getOpcode(Inst)) { in DecodeUnsignedLdStInstruction()
1017 switch (MCInst_getOpcode(Inst)) { in DecodeSignedLdStInstruction()
1070 switch (MCInst_getOpcode(Inst)) { in DecodeSignedLdStInstruction()
1197 unsigned Opcode = MCInst_getOpcode(Inst); in DecodeExclusiveLdStInstruction()
1274 unsigned Opcode = MCInst_getOpcode(Inst); in DecodePairLdStInstruction()
1409 switch (MCInst_getOpcode(Inst)) { in DecodeAddSubERegInstruction()
[all …]
DAArch64InstPrinter.c69 unsigned Opcode = MCInst_getOpcode(MI); in AArch64_printInst()
1287 unsigned Opcode = MCInst_getOpcode(MI); in printBarrierOption()
DAArch64GenAsmWriter.inc5195 uint64_t Bits1 = OpInfo[MCInst_getOpcode(MI)];
5196 uint64_t Bits2 = OpInfo2[MCInst_getOpcode(MI)];
7083 switch (MCInst_getOpcode(MI)) {
/external/capstone/arch/Sparc/
DSparcInstPrinter.c107 switch (MCInst_getOpcode(MI)) { in printSparcAliasInstr()
149 switch(MCInst_getOpcode(MI)) { in printSparcAliasInstr()
328 switch (MCInst_getOpcode(MI)) { in printCCOperand()
377 switch(MCInst_getOpcode(MI)) { in Sparc_printInst()
DSparcGenAsmWriter.inc828 uint32_t Bits = OpInfo[MCInst_getOpcode(MI)];
1224 switch (MCInst_getOpcode(MI)) {
/external/capstone/
DMCInst.h120 unsigned MCInst_getOpcode(const MCInst*);
DMCInst.c54 unsigned MCInst_getOpcode(const MCInst *inst) in MCInst_getOpcode() function
/external/capstone/arch/Mips/
DMipsDisassembler.c896 if (MCInst_getOpcode(Inst) == Mips_SC){ in DecodeMem()
944 switch(MCInst_getOpcode(Inst)) { in DecodeMSA128Mem()
980 if (MCInst_getOpcode(Inst) == Mips_SC_MM) in DecodeMemMMImm12()
1068 if (MCInst_getOpcode(Inst) == Mips_SC_R6 || in DecodeSpecial3LlSc()
1069 MCInst_getOpcode(Inst) == Mips_SCD_R6) { in DecodeSpecial3LlSc()
DMipsInstPrinter.c159 switch (MCInst_getOpcode(MI)) { in Mips_printInst()
342 switch (MCInst_getOpcode(MI)) { in printAlias()
DMipsGenAsmWriter.inc4505 uint64_t Bits1 = OpInfo[MCInst_getOpcode(MI)];
4506 uint64_t Bits2 = OpInfo2[MCInst_getOpcode(MI)];
5066 switch (MCInst_getOpcode(MI)) {
/external/capstone/arch/XCore/
DXCoreGenAsmWriter.inc418 uint32_t Bits = OpInfo[MCInst_getOpcode(MI)];
/external/capstone/arch/SystemZ/
DSystemZGenAsmWriter.inc1549 uint32_t Bits = OpInfo[MCInst_getOpcode(MI)];

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