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1 /*
2  *  linux/include/asm-arm/arch-pxa/pxa-regs.h
3  *
4  *  Author:	Nicolas Pitre
5  *  Created:	Jun 15, 2001
6  *  Copyright:	MontaVista Software Inc.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  *
12  * - 2003/01/20: Robert Schwebel <r.schwebel@pengutronix.de
13  *   Original file taken from linux-2.4.19-rmk4-pxa1. Added some definitions.
14  *   Added include for hardware.h (for __REG definition)
15  */
16 #ifndef _PXA_REGS_H_
17 #define _PXA_REGS_H_
18 
19 #include "bitfield.h"
20 #include "hardware.h"
21 
22 /* FIXME hack so that SA-1111.h will work [cb] */
23 
24 #ifndef __ASSEMBLY__
25 typedef unsigned short	Word16 ;
26 typedef unsigned int	Word32 ;
27 typedef Word32		Word ;
28 typedef Word		Quad [4] ;
29 typedef void		*Address ;
30 typedef void		(*ExcpHndlr) (void) ;
31 #endif
32 
33 /*
34  * PXA Chip selects
35  */
36 #ifdef CONFIG_CPU_MONAHANS
37 #define PXA_CS0_PHYS   0x00000000 /* for both small and large same start */
38 #define PXA_CS1_PHYS   0x04000000 /* Small partition start address (64MB) */
39 #define PXA_CS1_LPHYS  0x30000000 /* Large partition start address (256MB) */
40 #define PXA_CS2_PHYS   0x10000000 /* (64MB) */
41 #define PXA_CS3_PHYS   0x14000000 /* (64MB) */
42 #define PXA_PCMCIA_PHYS        0x20000000 /* (256MB) */
43 #else
44 #define PXA_CS0_PHYS	0x00000000
45 #define PXA_CS1_PHYS	0x04000000
46 #define PXA_CS2_PHYS	0x08000000
47 #define PXA_CS3_PHYS	0x0C000000
48 #define PXA_CS4_PHYS	0x10000000
49 #define PXA_CS5_PHYS	0x14000000
50 #endif /* CONFIG_CPU_MONAHANS */
51 
52 /*
53  * Personal Computer Memory Card International Association (PCMCIA) sockets
54  */
55 #define PCMCIAPrtSp	0x04000000	/* PCMCIA Partition Space [byte]   */
56 #define PCMCIASp	(4*PCMCIAPrtSp) /* PCMCIA Space [byte]		   */
57 #define PCMCIAIOSp	PCMCIAPrtSp	/* PCMCIA I/O Space [byte]	   */
58 #define PCMCIAAttrSp	PCMCIAPrtSp	/* PCMCIA Attribute Space [byte]   */
59 #define PCMCIAMemSp	PCMCIAPrtSp	/* PCMCIA Memory Space [byte]	   */
60 
61 #ifndef CONFIG_CPU_MONAHANS             /* Monahans supports only one slot */
62 #define PCMCIA0Sp	PCMCIASp	/* PCMCIA 0 Space [byte]	   */
63 #define PCMCIA0IOSp	PCMCIAIOSp	/* PCMCIA 0 I/O Space [byte]	   */
64 #define PCMCIA0AttrSp	PCMCIAAttrSp	/* PCMCIA 0 Attribute Space [byte] */
65 #define PCMCIA0MemSp	PCMCIAMemSp	/* PCMCIA 0 Memory Space [byte]	   */
66 #endif
67 
68 #define PCMCIA1Sp	PCMCIASp	/* PCMCIA 1 Space [byte]	   */
69 #define PCMCIA1IOSp	PCMCIAIOSp	/* PCMCIA 1 I/O Space [byte]	   */
70 #define PCMCIA1AttrSp	PCMCIAAttrSp	/* PCMCIA 1 Attribute Space [byte] */
71 #define PCMCIA1MemSp	PCMCIAMemSp	/* PCMCIA 1 Memory Space [byte]	   */
72 
73 #define _PCMCIA(Nb)			/* PCMCIA [0..1]		   */ \
74 			(0x20000000 + (Nb)*PCMCIASp)
75 #define _PCMCIAIO(Nb)	_PCMCIA (Nb)	/* PCMCIA I/O [0..1]		   */
76 #define _PCMCIAAttr(Nb)			/* PCMCIA Attribute [0..1]	   */ \
77 			(_PCMCIA (Nb) + 2*PCMCIAPrtSp)
78 #define _PCMCIAMem(Nb)			/* PCMCIA Memory [0..1]		   */ \
79 			(_PCMCIA (Nb) + 3*PCMCIAPrtSp)
80 
81 #define _PCMCIA0	_PCMCIA (0)	/* PCMCIA 0			   */
82 #define _PCMCIA0IO	_PCMCIAIO (0)	/* PCMCIA 0 I/O			   */
83 #define _PCMCIA0Attr	_PCMCIAAttr (0) /* PCMCIA 0 Attribute		   */
84 #define _PCMCIA0Mem	_PCMCIAMem (0)	/* PCMCIA 0 Memory		   */
85 
86 #ifndef CONFIG_CPU_MONAHANS             /* Monahans supports only one slot */
87 #define _PCMCIA1	_PCMCIA (1)	/* PCMCIA 1			   */
88 #define _PCMCIA1IO	_PCMCIAIO (1)	/* PCMCIA 1 I/O			   */
89 #define _PCMCIA1Attr	_PCMCIAAttr (1) /* PCMCIA 1 Attribute		   */
90 #define _PCMCIA1Mem	_PCMCIAMem (1)	/* PCMCIA 1 Memory		   */
91 #endif
92 
93 /*
94  * DMA Controller
95  */
96 #define DCSR0		0x40000000  /* DMA Control / Status Register for Channel 0 */
97 #define DCSR1		0x40000004  /* DMA Control / Status Register for Channel 1 */
98 #define DCSR2		0x40000008  /* DMA Control / Status Register for Channel 2 */
99 #define DCSR3		0x4000000c  /* DMA Control / Status Register for Channel 3 */
100 #define DCSR4		0x40000010  /* DMA Control / Status Register for Channel 4 */
101 #define DCSR5		0x40000014  /* DMA Control / Status Register for Channel 5 */
102 #define DCSR6		0x40000018  /* DMA Control / Status Register for Channel 6 */
103 #define DCSR7		0x4000001c  /* DMA Control / Status Register for Channel 7 */
104 #define DCSR8		0x40000020  /* DMA Control / Status Register for Channel 8 */
105 #define DCSR9		0x40000024  /* DMA Control / Status Register for Channel 9 */
106 #define DCSR10		0x40000028  /* DMA Control / Status Register for Channel 10 */
107 #define DCSR11		0x4000002c  /* DMA Control / Status Register for Channel 11 */
108 #define DCSR12		0x40000030  /* DMA Control / Status Register for Channel 12 */
109 #define DCSR13		0x40000034  /* DMA Control / Status Register for Channel 13 */
110 #define DCSR14		0x40000038  /* DMA Control / Status Register for Channel 14 */
111 #define DCSR15		0x4000003c  /* DMA Control / Status Register for Channel 15 */
112 #if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
113 #define DCSR16		0x40000040  /* DMA Control / Status Register for Channel 16 */
114 #define DCSR17		0x40000044  /* DMA Control / Status Register for Channel 17 */
115 #define DCSR18		0x40000048  /* DMA Control / Status Register for Channel 18 */
116 #define DCSR19		0x4000004c  /* DMA Control / Status Register for Channel 19 */
117 #define DCSR20		0x40000050  /* DMA Control / Status Register for Channel 20 */
118 #define DCSR21		0x40000054  /* DMA Control / Status Register for Channel 21 */
119 #define DCSR22		0x40000058  /* DMA Control / Status Register for Channel 22 */
120 #define DCSR23		0x4000005c  /* DMA Control / Status Register for Channel 23 */
121 #define DCSR24		0x40000060  /* DMA Control / Status Register for Channel 24 */
122 #define DCSR25		0x40000064  /* DMA Control / Status Register for Channel 25 */
123 #define DCSR26		0x40000068  /* DMA Control / Status Register for Channel 26 */
124 #define DCSR27		0x4000006c  /* DMA Control / Status Register for Channel 27 */
125 #define DCSR28		0x40000070  /* DMA Control / Status Register for Channel 28 */
126 #define DCSR29		0x40000074  /* DMA Control / Status Register for Channel 29 */
127 #define DCSR30		0x40000078  /* DMA Control / Status Register for Channel 30 */
128 #define DCSR31		0x4000007c  /* DMA Control / Status Register for Channel 31 */
129 #endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */
130 
131 #define DCSR(x)		(0x40000000 | ((x) << 2))
132 
133 #define DCSR_RUN	(1 << 31)	/* Run Bit (read / write) */
134 #define DCSR_NODESC	(1 << 30)	/* No-Descriptor Fetch (read / write) */
135 #define DCSR_STOPIRQEN	(1 << 29)	/* Stop Interrupt Enable (read / write) */
136 
137 #if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
138 #define DCSR_EORIRQEN	(1 << 28)	/* End of Receive Interrupt Enable (R/W) */
139 #define DCSR_EORJMPEN	(1 << 27)	/* Jump to next descriptor on EOR */
140 #define DCSR_EORSTOPEN	(1 << 26)	/* STOP on an EOR */
141 #define DCSR_SETCMPST	(1 << 25)	/* Set Descriptor Compare Status */
142 #define DCSR_CLRCMPST	(1 << 24)	/* Clear Descriptor Compare Status */
143 #define DCSR_CMPST	(1 << 10)	/* The Descriptor Compare Status */
144 #define DCSR_ENRINTR	(1 << 9)	/* The end of Receive */
145 #endif
146 
147 #define DCSR_REQPEND	(1 << 8)	/* Request Pending (read-only) */
148 #define DCSR_STOPSTATE	(1 << 3)	/* Stop State (read-only) */
149 #define DCSR_ENDINTR	(1 << 2)	/* End Interrupt (read / write) */
150 #define DCSR_STARTINTR	(1 << 1)	/* Start Interrupt (read / write) */
151 #define DCSR_BUSERR	(1 << 0)	/* Bus Error Interrupt (read / write) */
152 
153 #define DINT		0x400000f0  /* DMA Interrupt Register */
154 
155 #define DRCMR0		0x40000100  /* Request to Channel Map Register for DREQ 0 */
156 #define DRCMR1		0x40000104  /* Request to Channel Map Register for DREQ 1 */
157 #define DRCMR2		0x40000108  /* Request to Channel Map Register for I2S receive Request */
158 #define DRCMR3		0x4000010c  /* Request to Channel Map Register for I2S transmit Request */
159 #define DRCMR4		0x40000110  /* Request to Channel Map Register for BTUART receive Request */
160 #define DRCMR5		0x40000114  /* Request to Channel Map Register for BTUART transmit Request. */
161 #define DRCMR6		0x40000118  /* Request to Channel Map Register for FFUART receive Request */
162 #define DRCMR7		0x4000011c  /* Request to Channel Map Register for FFUART transmit Request */
163 #define DRCMR8		0x40000120  /* Request to Channel Map Register for AC97 microphone Request */
164 #define DRCMR9		0x40000124  /* Request to Channel Map Register for AC97 modem receive Request */
165 #define DRCMR10		0x40000128  /* Request to Channel Map Register for AC97 modem transmit Request */
166 #define DRCMR11		0x4000012c  /* Request to Channel Map Register for AC97 audio receive Request */
167 #define DRCMR12		0x40000130  /* Request to Channel Map Register for AC97 audio transmit Request */
168 #define DRCMR13		0x40000134  /* Request to Channel Map Register for SSP receive Request */
169 #define DRCMR14		0x40000138  /* Request to Channel Map Register for SSP transmit Request */
170 #define DRCMR15		0x4000013c  /* Reserved */
171 #define DRCMR16		0x40000140  /* Reserved */
172 #define DRCMR17		0x40000144  /* Request to Channel Map Register for ICP receive Request */
173 #define DRCMR18		0x40000148  /* Request to Channel Map Register for ICP transmit Request */
174 #define DRCMR19		0x4000014c  /* Request to Channel Map Register for STUART receive Request */
175 #define DRCMR20		0x40000150  /* Request to Channel Map Register for STUART transmit Request */
176 #define DRCMR21		0x40000154  /* Request to Channel Map Register for MMC receive Request */
177 #define DRCMR22		0x40000158  /* Request to Channel Map Register for MMC transmit Request */
178 #define DRCMR23		0x4000015c  /* Reserved */
179 #define DRCMR24		0x40000160  /* Reserved */
180 #define DRCMR25		0x40000164  /* Request to Channel Map Register for USB endpoint 1 Request */
181 #define DRCMR26		0x40000168  /* Request to Channel Map Register for USB endpoint 2 Request */
182 #define DRCMR27		0x4000016C  /* Request to Channel Map Register for USB endpoint 3 Request */
183 #define DRCMR28		0x40000170  /* Request to Channel Map Register for USB endpoint 4 Request */
184 #define DRCMR29		0x40000174  /* Reserved */
185 #define DRCMR30		0x40000178  /* Request to Channel Map Register for USB endpoint 6 Request */
186 #define DRCMR31		0x4000017C  /* Request to Channel Map Register for USB endpoint 7 Request */
187 #define DRCMR32		0x40000180  /* Request to Channel Map Register for USB endpoint 8 Request */
188 #define DRCMR33		0x40000184  /* Request to Channel Map Register for USB endpoint 9 Request */
189 #define DRCMR34		0x40000188  /* Reserved */
190 #define DRCMR35		0x4000018C  /* Request to Channel Map Register for USB endpoint 11 Request */
191 #define DRCMR36		0x40000190  /* Request to Channel Map Register for USB endpoint 12 Request */
192 #define DRCMR37		0x40000194  /* Request to Channel Map Register for USB endpoint 13 Request */
193 #define DRCMR38		0x40000198  /* Request to Channel Map Register for USB endpoint 14 Request */
194 #define DRCMR39		0x4000019C  /* Reserved */
195 
196 #define DRCMR68		       0x40001110  /* Request to Channel Map Register for Camera FIFO 0 Request */
197 #define DRCMR69		       0x40001114  /* Request to Channel Map Register for Camera FIFO 1 Request */
198 #define DRCMR70		       0x40001118  /* Request to Channel Map Register for Camera FIFO 2 Request */
199 
200 #define DRCMRRXSADR	DRCMR2
201 #define DRCMRTXSADR	DRCMR3
202 #define DRCMRRXBTRBR	DRCMR4
203 #define DRCMRTXBTTHR	DRCMR5
204 #define DRCMRRXFFRBR	DRCMR6
205 #define DRCMRTXFFTHR	DRCMR7
206 #define DRCMRRXMCDR	DRCMR8
207 #define DRCMRRXMODR	DRCMR9
208 #define DRCMRTXMODR	DRCMR10
209 #define DRCMRRXPCDR	DRCMR11
210 #define DRCMRTXPCDR	DRCMR12
211 #define DRCMRRXSSDR	DRCMR13
212 #define DRCMRTXSSDR	DRCMR14
213 #define DRCMRRXICDR	DRCMR17
214 #define DRCMRTXICDR	DRCMR18
215 #define DRCMRRXSTRBR	DRCMR19
216 #define DRCMRTXSTTHR	DRCMR20
217 #define DRCMRRXMMC	DRCMR21
218 #define DRCMRTXMMC	DRCMR22
219 
220 #define DRCMR_MAPVLD	(1 << 7)	/* Map Valid (read / write) */
221 #define DRCMR_CHLNUM	0x0f		/* mask for Channel Number (read / write) */
222 
223 #define DDADR0		0x40000200  /* DMA Descriptor Address Register Channel 0 */
224 #define DSADR0		0x40000204  /* DMA Source Address Register Channel 0 */
225 #define DTADR0		0x40000208  /* DMA Target Address Register Channel 0 */
226 #define DCMD0		0x4000020c  /* DMA Command Address Register Channel 0 */
227 #define DDADR1		0x40000210  /* DMA Descriptor Address Register Channel 1 */
228 #define DSADR1		0x40000214  /* DMA Source Address Register Channel 1 */
229 #define DTADR1		0x40000218  /* DMA Target Address Register Channel 1 */
230 #define DCMD1		0x4000021c  /* DMA Command Address Register Channel 1 */
231 #define DDADR2		0x40000220  /* DMA Descriptor Address Register Channel 2 */
232 #define DSADR2		0x40000224  /* DMA Source Address Register Channel 2 */
233 #define DTADR2		0x40000228  /* DMA Target Address Register Channel 2 */
234 #define DCMD2		0x4000022c  /* DMA Command Address Register Channel 2 */
235 #define DDADR3		0x40000230  /* DMA Descriptor Address Register Channel 3 */
236 #define DSADR3		0x40000234  /* DMA Source Address Register Channel 3 */
237 #define DTADR3		0x40000238  /* DMA Target Address Register Channel 3 */
238 #define DCMD3		0x4000023c  /* DMA Command Address Register Channel 3 */
239 #define DDADR4		0x40000240  /* DMA Descriptor Address Register Channel 4 */
240 #define DSADR4		0x40000244  /* DMA Source Address Register Channel 4 */
241 #define DTADR4		0x40000248  /* DMA Target Address Register Channel 4 */
242 #define DCMD4		0x4000024c  /* DMA Command Address Register Channel 4 */
243 #define DDADR5		0x40000250  /* DMA Descriptor Address Register Channel 5 */
244 #define DSADR5		0x40000254  /* DMA Source Address Register Channel 5 */
245 #define DTADR5		0x40000258  /* DMA Target Address Register Channel 5 */
246 #define DCMD5		0x4000025c  /* DMA Command Address Register Channel 5 */
247 #define DDADR6		0x40000260  /* DMA Descriptor Address Register Channel 6 */
248 #define DSADR6		0x40000264  /* DMA Source Address Register Channel 6 */
249 #define DTADR6		0x40000268  /* DMA Target Address Register Channel 6 */
250 #define DCMD6		0x4000026c  /* DMA Command Address Register Channel 6 */
251 #define DDADR7		0x40000270  /* DMA Descriptor Address Register Channel 7 */
252 #define DSADR7		0x40000274  /* DMA Source Address Register Channel 7 */
253 #define DTADR7		0x40000278  /* DMA Target Address Register Channel 7 */
254 #define DCMD7		0x4000027c  /* DMA Command Address Register Channel 7 */
255 #define DDADR8		0x40000280  /* DMA Descriptor Address Register Channel 8 */
256 #define DSADR8		0x40000284  /* DMA Source Address Register Channel 8 */
257 #define DTADR8		0x40000288  /* DMA Target Address Register Channel 8 */
258 #define DCMD8		0x4000028c  /* DMA Command Address Register Channel 8 */
259 #define DDADR9		0x40000290  /* DMA Descriptor Address Register Channel 9 */
260 #define DSADR9		0x40000294  /* DMA Source Address Register Channel 9 */
261 #define DTADR9		0x40000298  /* DMA Target Address Register Channel 9 */
262 #define DCMD9		0x4000029c  /* DMA Command Address Register Channel 9 */
263 #define DDADR10		0x400002a0  /* DMA Descriptor Address Register Channel 10 */
264 #define DSADR10		0x400002a4  /* DMA Source Address Register Channel 10 */
265 #define DTADR10		0x400002a8  /* DMA Target Address Register Channel 10 */
266 #define DCMD10		0x400002ac  /* DMA Command Address Register Channel 10 */
267 #define DDADR11		0x400002b0  /* DMA Descriptor Address Register Channel 11 */
268 #define DSADR11		0x400002b4  /* DMA Source Address Register Channel 11 */
269 #define DTADR11		0x400002b8  /* DMA Target Address Register Channel 11 */
270 #define DCMD11		0x400002bc  /* DMA Command Address Register Channel 11 */
271 #define DDADR12		0x400002c0  /* DMA Descriptor Address Register Channel 12 */
272 #define DSADR12		0x400002c4  /* DMA Source Address Register Channel 12 */
273 #define DTADR12		0x400002c8  /* DMA Target Address Register Channel 12 */
274 #define DCMD12		0x400002cc  /* DMA Command Address Register Channel 12 */
275 #define DDADR13		0x400002d0  /* DMA Descriptor Address Register Channel 13 */
276 #define DSADR13		0x400002d4  /* DMA Source Address Register Channel 13 */
277 #define DTADR13		0x400002d8  /* DMA Target Address Register Channel 13 */
278 #define DCMD13		0x400002dc  /* DMA Command Address Register Channel 13 */
279 #define DDADR14		0x400002e0  /* DMA Descriptor Address Register Channel 14 */
280 #define DSADR14		0x400002e4  /* DMA Source Address Register Channel 14 */
281 #define DTADR14		0x400002e8  /* DMA Target Address Register Channel 14 */
282 #define DCMD14		0x400002ec  /* DMA Command Address Register Channel 14 */
283 #define DDADR15		0x400002f0  /* DMA Descriptor Address Register Channel 15 */
284 #define DSADR15		0x400002f4  /* DMA Source Address Register Channel 15 */
285 #define DTADR15		0x400002f8  /* DMA Target Address Register Channel 15 */
286 #define DCMD15		0x400002fc  /* DMA Command Address Register Channel 15 */
287 
288 #define DDADR(x)	(0x40000200 | ((x) << 4))
289 #define DSADR(x)	(0x40000204 | ((x) << 4))
290 #define DTADR(x)	(0x40000208 | ((x) << 4))
291 #define DCMD(x)		(0x4000020c | ((x) << 4))
292 
293 #define DDADR_DESCADDR	0xfffffff0	/* Address of next descriptor (mask) */
294 #define DDADR_STOP	(1 << 0)	/* Stop (read / write) */
295 
296 #define DCMD_INCSRCADDR (1 << 31)	/* Source Address Increment Setting. */
297 #define DCMD_INCTRGADDR (1 << 30)	/* Target Address Increment Setting. */
298 #define DCMD_FLOWSRC	(1 << 29)	/* Flow Control by the source. */
299 #define DCMD_FLOWTRG	(1 << 28)	/* Flow Control by the target. */
300 #define DCMD_STARTIRQEN (1 << 22)	/* Start Interrupt Enable */
301 #define DCMD_ENDIRQEN	(1 << 21)	/* End Interrupt Enable */
302 #define DCMD_ENDIAN	(1 << 18)	/* Device Endian-ness. */
303 #define DCMD_BURST8	(1 << 16)	/* 8 byte burst */
304 #define DCMD_BURST16	(2 << 16)	/* 16 byte burst */
305 #define DCMD_BURST32	(3 << 16)	/* 32 byte burst */
306 #define DCMD_WIDTH1	(1 << 14)	/* 1 byte width */
307 #define DCMD_WIDTH2	(2 << 14)	/* 2 byte width (HalfWord) */
308 #define DCMD_WIDTH4	(3 << 14)	/* 4 byte width (Word) */
309 #define DCMD_LENGTH	0x01fff		/* length mask (max = 8K - 1) */
310 
311 /* default combinations */
312 #define DCMD_RXPCDR	(DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
313 #define DCMD_RXMCDR	(DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
314 #define DCMD_TXPCDR	(DCMD_INCSRCADDR|DCMD_FLOWTRG|DCMD_BURST32|DCMD_WIDTH4)
315 
316 /******************************************************************************/
317 /*
318  * IrSR (Infrared Selection Register)
319  */
320 #define IrSR_OFFSET 0x20
321 
322 #define IrSR_RXPL_NEG_IS_ZERO (1<<4)
323 #define IrSR_RXPL_POS_IS_ZERO 0x0
324 #define IrSR_TXPL_NEG_IS_ZERO (1<<3)
325 #define IrSR_TXPL_POS_IS_ZERO 0x0
326 #define IrSR_XMODE_PULSE_1_6  (1<<2)
327 #define IrSR_XMODE_PULSE_3_16 0x0
328 #define IrSR_RCVEIR_IR_MODE   (1<<1)
329 #define IrSR_RCVEIR_UART_MODE 0x0
330 #define IrSR_XMITIR_IR_MODE   (1<<0)
331 #define IrSR_XMITIR_UART_MODE 0x0
332 
333 #define IrSR_IR_RECEIVE_ON (\
334 		IrSR_RXPL_NEG_IS_ZERO | \
335 		IrSR_TXPL_POS_IS_ZERO | \
336 		IrSR_XMODE_PULSE_3_16 | \
337 		IrSR_RCVEIR_IR_MODE   | \
338 		IrSR_XMITIR_UART_MODE)
339 
340 #define IrSR_IR_TRANSMIT_ON (\
341 		IrSR_RXPL_NEG_IS_ZERO | \
342 		IrSR_TXPL_POS_IS_ZERO | \
343 		IrSR_XMODE_PULSE_3_16 | \
344 		IrSR_RCVEIR_UART_MODE | \
345 		IrSR_XMITIR_IR_MODE)
346 
347 /*
348  * Serial Audio Controller
349  */
350 /* FIXME the audio defines collide w/ the SA1111 defines.  I don't like these
351  * short defines because there is too much chance of namespace collision
352  */
353 #define SACR0		0x40400000  /*  Global Control Register */
354 #define SACR1		0x40400004  /*  Serial Audio I 2 S/MSB-Justified Control Register */
355 #define SASR0		0x4040000C  /*  Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
356 #define SAIMR		0x40400014  /*  Serial Audio Interrupt Mask Register */
357 #define SAICR		0x40400018  /*  Serial Audio Interrupt Clear Register */
358 #define SADIV		0x40400060  /*  Audio Clock Divider Register. */
359 #define SADR		0x40400080  /*  Serial Audio Data Register (TX and RX FIFO access Register). */
360 
361 /*
362  * AC97 Controller registers
363  */
364 #define POCR		0x40500000  /* PCM Out Control Register */
365 #define POCR_FEIE	(1 << 3)	/* FIFO Error Interrupt Enable */
366 
367 #define PICR		0x40500004  /* PCM In Control Register */
368 #define PICR_FEIE	(1 << 3)	/* FIFO Error Interrupt Enable */
369 
370 #define MCCR		0x40500008  /* Mic In Control Register */
371 #define MCCR_FEIE	(1 << 3)	/* FIFO Error Interrupt Enable */
372 
373 #define GCR		0x4050000C  /* Global Control Register */
374 #define GCR_CDONE_IE	(1 << 19)	/* Command Done Interrupt Enable */
375 #define GCR_SDONE_IE	(1 << 18)	/* Status Done Interrupt Enable */
376 #define GCR_SECRDY_IEN	(1 << 9)	/* Secondary Ready Interrupt Enable */
377 #define GCR_PRIRDY_IEN	(1 << 8)	/* Primary Ready Interrupt Enable */
378 #define GCR_SECRES_IEN	(1 << 5)	/* Secondary Resume Interrupt Enable */
379 #define GCR_PRIRES_IEN	(1 << 4)	/* Primary Resume Interrupt Enable */
380 #define GCR_ACLINK_OFF	(1 << 3)	/* AC-link Shut Off */
381 #define GCR_WARM_RST	(1 << 2)	/* AC97 Warm Reset */
382 #define GCR_COLD_RST	(1 << 1)	/* AC'97 Cold Reset (0 = active) */
383 #define GCR_GIE		(1 << 0)	/* Codec GPI Interrupt Enable */
384 
385 #define POSR		0x40500010  /* PCM Out Status Register */
386 #define POSR_FIFOE	(1 << 4)	/* FIFO error */
387 
388 #define PISR		0x40500014  /* PCM In Status Register */
389 #define PISR_FIFOE	(1 << 4)	/* FIFO error */
390 
391 #define MCSR		0x40500018  /* Mic In Status Register */
392 #define MCSR_FIFOE	(1 << 4)	/* FIFO error */
393 
394 #define GSR		0x4050001C  /* Global Status Register */
395 #define GSR_CDONE	(1 << 19)	/* Command Done */
396 #define GSR_SDONE	(1 << 18)	/* Status Done */
397 #define GSR_RDCS	(1 << 15)	/* Read Completion Status */
398 #define GSR_BIT3SLT12	(1 << 14)	/* Bit 3 of slot 12 */
399 #define GSR_BIT2SLT12	(1 << 13)	/* Bit 2 of slot 12 */
400 #define GSR_BIT1SLT12	(1 << 12)	/* Bit 1 of slot 12 */
401 #define GSR_SECRES	(1 << 11)	/* Secondary Resume Interrupt */
402 #define GSR_PRIRES	(1 << 10)	/* Primary Resume Interrupt */
403 #define GSR_SCR		(1 << 9)	/* Secondary Codec Ready */
404 #define GSR_PCR		(1 << 8)	/*  Primary Codec Ready */
405 #define GSR_MINT	(1 << 7)	/* Mic In Interrupt */
406 #define GSR_POINT	(1 << 6)	/* PCM Out Interrupt */
407 #define GSR_PIINT	(1 << 5)	/* PCM In Interrupt */
408 #define GSR_MOINT	(1 << 2)	/* Modem Out Interrupt */
409 #define GSR_MIINT	(1 << 1)	/* Modem In Interrupt */
410 #define GSR_GSCI	(1 << 0)	/* Codec GPI Status Change Interrupt */
411 
412 #define CAR		0x40500020  /* CODEC Access Register */
413 #define CAR_CAIP	(1 << 0)	/* Codec Access In Progress */
414 
415 #define PCDR		0x40500040  /* PCM FIFO Data Register */
416 #define MCDR		0x40500060  /* Mic-in FIFO Data Register */
417 
418 #define MOCR		0x40500100  /* Modem Out Control Register */
419 #define MOCR_FEIE	(1 << 3)	/* FIFO Error */
420 
421 #define MICR		0x40500108  /* Modem In Control Register */
422 #define MICR_FEIE	(1 << 3)	/* FIFO Error */
423 
424 #define MOSR		0x40500110  /* Modem Out Status Register */
425 #define MOSR_FIFOE	(1 << 4)	/* FIFO error */
426 
427 #define MISR		0x40500118  /* Modem In Status Register */
428 #define MISR_FIFOE	(1 << 4)	/* FIFO error */
429 
430 #define MODR		0x40500140  /* Modem FIFO Data Register */
431 
432 #define PAC_REG_BASE	0x40500200  /* Primary Audio Codec */
433 #define SAC_REG_BASE	0x40500300  /* Secondary Audio Codec */
434 #define PMC_REG_BASE	0x40500400  /* Primary Modem Codec */
435 #define SMC_REG_BASE	0x40500500  /* Secondary Modem Codec */
436 
437 
438 /*
439  * USB Device Controller
440  */
441 #if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
442 
443 #define UDCCR		0x40600000	/* UDC Control Register */
444 #define UDCCR_UDE	(1 << 0)		/* UDC enable */
445 #define UDCCR_UDA	(1 << 1)		/* UDC active */
446 #define UDCCR_RSM	(1 << 2)		/* Device resume */
447 #define UDCCR_EMCE	(1 << 3)		/* Endpoint Memory Configuration Error */
448 #define UDCCR_SMAC	(1 << 4)		/* Switch Endpoint Memory to Active Configuration */
449 #define UDCCR_RESIR	(1 << 29)		/* Resume interrupt request */
450 #define UDCCR_SUSIR	(1 << 28)		/* Suspend interrupt request */
451 #define UDCCR_SM	(1 << 28)		/* Suspend interrupt mask */
452 #define UDCCR_RSTIR	(1 << 27)		/* Reset interrupt request */
453 #define UDCCR_REM	(1 << 27)		/* Reset interrupt mask */
454 #define UDCCR_RM	(1 << 29)		/* resume interrupt mask */
455 #define UDCCR_SRM	(UDCCR_SM|UDCCR_RM)
456 #define UDCCR_OEN	(1 << 31)		/* On-the-Go Enable */
457 #define UDCCR_AALTHNP	(1 << 30)		/* A-device Alternate Host Negotiation Protocol Port Support */
458 #define UDCCR_AHNP	(1 << 29)		/* A-device Host Negotiation Protocol Support */
459 #define UDCCR_BHNP	(1 << 28)		/* B-device Host Negotiation Protocol Enable */
460 #define UDCCR_DWRE	(1 << 16)		/* Device Remote Wake-up Enable */
461 #define UDCCR_ACN	(0x03 << 11)		/* Active UDC configuration Number */
462 #define UDCCR_ACN_S	11
463 #define UDCCR_AIN	(0x07 << 8)		/* Active UDC interface Number */
464 #define UDCCR_AIN_S	8
465 #define UDCCR_AAISN	(0x07 << 5)		/* Active UDC Alternate Interface  Setting Number */
466 #define UDCCR_AAISN_S	5
467 
468 #define UDCCS0		0x40600100	/* UDC Endpoint 0 Control/Status Register */
469 #define UDCCS0_OPR	(1 << 0)		/* OUT packet ready */
470 #define UDCCS0_IPR	(1 << 1)		/* IN packet ready */
471 #define UDCCS0_FTF	(1 << 2)		/* Flush Tx FIFO */
472 #define UDCCS0_DRWF	(1 << 16)		/* Device remote wakeup feature */
473 #define UDCCS0_SST	(1 << 4)		/* Sent stall */
474 #define UDCCS0_FST	(1 << 5)		/* Force stall */
475 #define UDCCS0_RNE	(1 << 6)		/* Receive FIFO no empty */
476 #define UDCCS0_SA	(1 << 7)		/* Setup active */
477 
478 /* Bulk IN - Endpoint 1,6,11 */
479 #define UDCCS1		0x40600104  /* UDC Endpoint 1 (IN) Control/Status Register */
480 #define UDCCS6		0x40600028  /* UDC Endpoint 6 (IN) Control/Status Register */
481 #define UDCCS11		0x4060003C  /* UDC Endpoint 11 (IN) Control/Status Register */
482 
483 #define UDCCS_BI_TFS	(1 << 0)	/* Transmit FIFO service */
484 #define UDCCS_BI_TPC	(1 << 1)	/* Transmit packet complete */
485 #define UDCCS_BI_FTF	(1 << 8)	/* Flush Tx FIFO */
486 #define UDCCS_BI_TUR	(1 << 3)	/* Transmit FIFO underrun */
487 #define UDCCS_BI_SST	(1 << 4)	/* Sent stall */
488 #define UDCCS_BI_FST	(1 << 5)	/* Force stall */
489 #define UDCCS_BI_TSP	(1 << 7)	/* Transmit short packet */
490 
491 /* Bulk OUT - Endpoint 2,7,12 */
492 #define UDCCS2		0x40600108  /* UDC Endpoint 2 (OUT) Control/Status Register */
493 #define UDCCS7		0x4060002C  /* UDC Endpoint 7 (OUT) Control/Status Register */
494 #define UDCCS12		0x40600040  /* UDC Endpoint 12 (OUT) Control/Status Register */
495 
496 #define UDCCS_BO_RFS	(1 << 0)	/* Receive FIFO service */
497 #define UDCCS_BO_RPC	(1 << 1)	/* Receive packet complete */
498 #define UDCCS_BO_DME	(1 << 3)	/* DMA enable */
499 #define UDCCS_BO_SST	(1 << 4)	/* Sent stall */
500 #define UDCCS_BO_FST	(1 << 5)	/* Force stall */
501 #define UDCCS_BO_RNE	(1 << 6)	/* Receive FIFO not empty */
502 #define UDCCS_BO_RSP	(1 << 7)	/* Receive short packet */
503 
504 /* Isochronous IN - Endpoint 3,8,13 */
505 #define UDCCS3		0x4060001C  /* UDC Endpoint 3 (IN) Control/Status Register */
506 #define UDCCS8		0x40600030  /* UDC Endpoint 8 (IN) Control/Status Register */
507 #define UDCCS13		0x40600044  /* UDC Endpoint 13 (IN) Control/Status Register */
508 
509 #define UDCCS_II_TFS	(1 << 0)	/* Transmit FIFO service */
510 #define UDCCS_II_TPC	(1 << 1)	/* Transmit packet complete */
511 #define UDCCS_II_FTF	(1 << 2)	/* Flush Tx FIFO */
512 #define UDCCS_II_TUR	(1 << 3)	/* Transmit FIFO underrun */
513 #define UDCCS_II_TSP	(1 << 7)	/* Transmit short packet */
514 
515 /* Isochronous OUT - Endpoint 4,9,14 */
516 #define UDCCS4		0x40600020  /* UDC Endpoint 4 (OUT) Control/Status Register */
517 #define UDCCS9		0x40600034  /* UDC Endpoint 9 (OUT) Control/Status Register */
518 #define UDCCS14		0x40600048  /* UDC Endpoint 14 (OUT) Control/Status Register */
519 
520 #define UDCCS_IO_RFS	(1 << 0)	/* Receive FIFO service */
521 #define UDCCS_IO_RPC	(1 << 1)	/* Receive packet complete */
522 #define UDCCS_IO_ROF	(1 << 3)	/* Receive overflow */
523 #define UDCCS_IO_DME	(1 << 3)	/* DMA enable */
524 #define UDCCS_IO_RNE	(1 << 6)	/* Receive FIFO not empty */
525 #define UDCCS_IO_RSP	(1 << 7)	/* Receive short packet */
526 
527 /* Interrupt IN - Endpoint 5,10,15 */
528 #define UDCCS5		0x40600024  /* UDC Endpoint 5 (Interrupt) Control/Status Register */
529 #define UDCCS10		0x40600038  /* UDC Endpoint 10 (Interrupt) Control/Status Register */
530 #define UDCCS15		0x4060004C  /* UDC Endpoint 15 (Interrupt) Control/Status Register */
531 
532 #define UDCCS_INT_TFS	(1 << 0)	/* Transmit FIFO service */
533 #define UDCCS_INT_TPC	(1 << 1)	/* Transmit packet complete */
534 #define UDCCS_INT_FTF	(1 << 2)	/* Flush Tx FIFO */
535 #define UDCCS_INT_TUR	(1 << 3)	/* Transmit FIFO underrun */
536 #define UDCCS_INT_SST	(1 << 4)	/* Sent stall */
537 #define UDCCS_INT_FST	(1 << 5)	/* Force stall */
538 #define UDCCS_INT_TSP	(1 << 7)	/* Transmit short packet */
539 
540 #define UFNRH		0x40600060  /* UDC Frame Number Register High */
541 #define UFNRL		0x40600014  /* UDC Frame Number Register Low */
542 #define UBCR2		0x40600208  /* UDC Byte Count Reg 2 */
543 #define UBCR4		0x4060006c  /* UDC Byte Count Reg 4 */
544 #define UBCR7		0x40600070  /* UDC Byte Count Reg 7 */
545 #define UBCR9		0x40600074  /* UDC Byte Count Reg 9 */
546 #define UBCR12		0x40600078  /* UDC Byte Count Reg 12 */
547 #define UBCR14		0x4060007c  /* UDC Byte Count Reg 14 */
548 #define UDDR0		0x40600300  /* UDC Endpoint 0 Data Register */
549 #define UDDR1		0x40600304  /* UDC Endpoint 1 Data Register */
550 #define UDDR2		0x40600308  /* UDC Endpoint 2 Data Register */
551 #define UDDR3		0x40600200  /* UDC Endpoint 3 Data Register */
552 #define UDDR4		0x40600400  /* UDC Endpoint 4 Data Register */
553 #define UDDR5		0x406000A0  /* UDC Endpoint 5 Data Register */
554 #define UDDR6		0x40600600  /* UDC Endpoint 6 Data Register */
555 #define UDDR7		0x40600680  /* UDC Endpoint 7 Data Register */
556 #define UDDR8		0x40600700  /* UDC Endpoint 8 Data Register */
557 #define UDDR9		0x40600900  /* UDC Endpoint 9 Data Register */
558 #define UDDR10		0x406000C0  /* UDC Endpoint 10 Data Register */
559 #define UDDR11		0x40600B00  /* UDC Endpoint 11 Data Register */
560 #define UDDR12		0x40600B80  /* UDC Endpoint 12 Data Register */
561 #define UDDR13		0x40600C00  /* UDC Endpoint 13 Data Register */
562 #define UDDR14		0x40600E00  /* UDC Endpoint 14 Data Register */
563 #define UDDR15		0x406000E0  /* UDC Endpoint 15 Data Register */
564 
565 #define UICR0		0x40600004  /* UDC Interrupt Control Register 0 */
566 
567 #define UICR0_IM0	(1 << 0)	/* Interrupt mask ep 0 */
568 #define UICR0_IM1	(1 << 1)	/* Interrupt mask ep 1 */
569 #define UICR0_IM2	(1 << 2)	/* Interrupt mask ep 2 */
570 #define UICR0_IM3	(1 << 3)	/* Interrupt mask ep 3 */
571 #define UICR0_IM4	(1 << 4)	/* Interrupt mask ep 4 */
572 #define UICR0_IM5	(1 << 5)	/* Interrupt mask ep 5 */
573 #define UICR0_IM6	(1 << 6)	/* Interrupt mask ep 6 */
574 #define UICR0_IM7	(1 << 7)	/* Interrupt mask ep 7 */
575 
576 #define UICR1		0x40600008  /* UDC Interrupt Control Register 1 */
577 
578 #define UICR1_IM8	(1 << 0)	/* Interrupt mask ep 8 */
579 #define UICR1_IM9	(1 << 1)	/* Interrupt mask ep 9 */
580 #define UICR1_IM10	(1 << 2)	/* Interrupt mask ep 10 */
581 #define UICR1_IM11	(1 << 3)	/* Interrupt mask ep 11 */
582 #define UICR1_IM12	(1 << 4)	/* Interrupt mask ep 12 */
583 #define UICR1_IM13	(1 << 5)	/* Interrupt mask ep 13 */
584 #define UICR1_IM14	(1 << 6)	/* Interrupt mask ep 14 */
585 #define UICR1_IM15	(1 << 7)	/* Interrupt mask ep 15 */
586 
587 #define USIR0		0x4060000C  /* UDC Status Interrupt Register 0 */
588 
589 #define USIR0_IR0	(1 << 0)	/* Interrup request ep 0 */
590 #define USIR0_IR1	(1 << 2)	/* Interrup request ep 1 */
591 #define USIR0_IR2	(1 << 4)	/* Interrup request ep 2 */
592 #define USIR0_IR3	(1 << 3)	/* Interrup request ep 3 */
593 #define USIR0_IR4	(1 << 4)	/* Interrup request ep 4 */
594 #define USIR0_IR5	(1 << 5)	/* Interrup request ep 5 */
595 #define USIR0_IR6	(1 << 6)	/* Interrup request ep 6 */
596 #define USIR0_IR7	(1 << 7)	/* Interrup request ep 7 */
597 
598 #define USIR1		0x40600010  /* UDC Status Interrupt Register 1 */
599 
600 #define USIR1_IR8	(1 << 0)	/* Interrup request ep 8 */
601 #define USIR1_IR9	(1 << 1)	/* Interrup request ep 9 */
602 #define USIR1_IR10	(1 << 2)	/* Interrup request ep 10 */
603 #define USIR1_IR11	(1 << 3)	/* Interrup request ep 11 */
604 #define USIR1_IR12	(1 << 4)	/* Interrup request ep 12 */
605 #define USIR1_IR13	(1 << 5)	/* Interrup request ep 13 */
606 #define USIR1_IR14	(1 << 6)	/* Interrup request ep 14 */
607 #define USIR1_IR15	(1 << 7)	/* Interrup request ep 15 */
608 
609 
610 #define UDCICR0         0x40600004	/* UDC Interrupt Control Register0 */
611 #define UDCICR1         0x40600008	/* UDC Interrupt Control Register1 */
612 #define UDCICR_FIFOERR	(1 << 1)			/* FIFO Error interrupt for EP */
613 #define UDCICR_PKTCOMPL (1 << 0)			/* Packet Complete interrupt for EP */
614 
615 #define UDCICR_INT(n, intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
616 #define UDCICR1_IECC	(1 << 31)	/* IntEn - Configuration Change */
617 #define UDCICR1_IESOF	(1 << 30)	/* IntEn - Start of Frame */
618 #define UDCICR1_IERU	(1 << 29)	/* IntEn - Resume */
619 #define UDCICR1_IESU	(1 << 28)	/* IntEn - Suspend */
620 #define UDCICR1_IERS	(1 << 27)	/* IntEn - Reset */
621 
622 #define UDCISR0         0x4060000C /* UDC Interrupt Status Register 0 */
623 #define UDCISR1         0x40600010 /* UDC Interrupt Status Register 1 */
624 #define UDCISR_INT(n, intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
625 #define UDCISR1_IRCC	(1 << 31)	/* IntEn - Configuration Change */
626 #define UDCISR1_IRSOF	(1 << 30)	/* IntEn - Start of Frame */
627 #define UDCISR1_IRRU	(1 << 29)	/* IntEn - Resume */
628 #define UDCISR1_IRSU	(1 << 28)	/* IntEn - Suspend */
629 #define UDCISR1_IRRS	(1 << 27)	/* IntEn - Reset */
630 
631 
632 #define UDCFNR			0x40600014 /* UDC Frame Number Register */
633 #define UDCOTGICR		0x40600018 /* UDC On-The-Go interrupt control */
634 #define UDCOTGICR_IESF		(1 << 24)	/* OTG SET_FEATURE command recvd */
635 #define UDCOTGICR_IEXR		(1 << 17)	/* Extra Transciever Interrupt Rising Edge Interrupt Enable */
636 #define UDCOTGICR_IEXF		(1 << 16)	/* Extra Transciever Interrupt Falling Edge Interrupt Enable */
637 #define UDCOTGICR_IEVV40R	(1 << 9)	/* OTG Vbus Valid 4.0V Rising Edge Interrupt Enable */
638 #define UDCOTGICR_IEVV40F	(1 << 8)	/* OTG Vbus Valid 4.0V Falling Edge Interrupt Enable */
639 #define UDCOTGICR_IEVV44R	(1 << 7)	/* OTG Vbus Valid 4.4V Rising Edge  Interrupt Enable */
640 #define UDCOTGICR_IEVV44F	(1 << 6)	/* OTG Vbus Valid 4.4V Falling Edge Interrupt Enable */
641 #define UDCOTGICR_IESVR		(1 << 5)	/* OTG Session Valid Rising Edge Interrupt Enable */
642 #define UDCOTGICR_IESVF		(1 << 4)	/* OTG Session Valid Falling Edge Interrupt Enable */
643 #define UDCOTGICR_IESDR		(1 << 3)	/* OTG A-Device SRP Detect Rising Edge Interrupt Enable */
644 #define UDCOTGICR_IESDF		(1 << 2)	/* OTG A-Device SRP Detect Falling  Edge Interrupt Enable */
645 #define UDCOTGICR_IEIDR		(1 << 1)	/* OTG ID Change Rising Edge Interrupt Enable */
646 #define UDCOTGICR_IEIDF		(1 << 0)	/* OTG ID Change Falling Edge Interrupt Enable */
647 
648 #define UDCCSN(x)	(0x40600100 + ((x) << 2))
649 #define UDCCSR0		0x40600100 /* UDC Control/Status register - Endpoint 0 */
650 
651 #define UDCCSR0_SA	(1 << 7)	/* Setup Active */
652 #define UDCCSR0_RNE	(1 << 6)	/* Receive FIFO Not Empty */
653 #define UDCCSR0_FST	(1 << 5)	/* Force Stall */
654 #define UDCCSR0_SST	(1 << 4)	/* Sent Stall */
655 #define UDCCSR0_DME	(1 << 3)	/* DMA Enable */
656 #define UDCCSR0_FTF	(1 << 2)	/* Flush Transmit FIFO */
657 #define UDCCSR0_IPR	(1 << 1)	/* IN Packet Ready */
658 #define UDCCSR0_OPC	(1 << 0)	/* OUT Packet Complete */
659 
660 #define UDCCSRA         0x40600104 /* UDC Control/Status register - Endpoint A */
661 #define UDCCSRB         0x40600108 /* UDC Control/Status register - Endpoint B */
662 #define UDCCSRC         0x4060010C /* UDC Control/Status register - Endpoint C */
663 #define UDCCSRD         0x40600110 /* UDC Control/Status register - Endpoint D */
664 #define UDCCSRE         0x40600114 /* UDC Control/Status register - Endpoint E */
665 #define UDCCSRF         0x40600118 /* UDC Control/Status register - Endpoint F */
666 #define UDCCSRG         0x4060011C /* UDC Control/Status register - Endpoint G */
667 #define UDCCSRH         0x40600120 /* UDC Control/Status register - Endpoint H */
668 #define UDCCSRI         0x40600124 /* UDC Control/Status register - Endpoint I */
669 #define UDCCSRJ         0x40600128 /* UDC Control/Status register - Endpoint J */
670 #define UDCCSRK         0x4060012C /* UDC Control/Status register - Endpoint K */
671 #define UDCCSRL         0x40600130 /* UDC Control/Status register - Endpoint L */
672 #define UDCCSRM         0x40600134 /* UDC Control/Status register - Endpoint M */
673 #define UDCCSRN         0x40600138 /* UDC Control/Status register - Endpoint N */
674 #define UDCCSRP         0x4060013C /* UDC Control/Status register - Endpoint P */
675 #define UDCCSRQ         0x40600140 /* UDC Control/Status register - Endpoint Q */
676 #define UDCCSRR         0x40600144 /* UDC Control/Status register - Endpoint R */
677 #define UDCCSRS         0x40600148 /* UDC Control/Status register - Endpoint S */
678 #define UDCCSRT         0x4060014C /* UDC Control/Status register - Endpoint T */
679 #define UDCCSRU         0x40600150 /* UDC Control/Status register - Endpoint U */
680 #define UDCCSRV         0x40600154 /* UDC Control/Status register - Endpoint V */
681 #define UDCCSRW         0x40600158 /* UDC Control/Status register - Endpoint W */
682 #define UDCCSRX         0x4060015C /* UDC Control/Status register - Endpoint X */
683 
684 #define UDCCSR_DPE	(1 << 9)	/* Data Packet Error */
685 #define UDCCSR_FEF	(1 << 8)	/* Flush Endpoint FIFO */
686 #define UDCCSR_SP	(1 << 7)	/* Short Packet Control/Status */
687 #define UDCCSR_BNE	(1 << 6)	/* Buffer Not Empty (IN endpoints) */
688 #define UDCCSR_BNF	(1 << 6)	/* Buffer Not Full (OUT endpoints) */
689 #define UDCCSR_FST	(1 << 5)	/* Force STALL */
690 #define UDCCSR_SST	(1 << 4)	/* Sent STALL */
691 #define UDCCSR_DME	(1 << 3)	/* DMA Enable */
692 #define UDCCSR_TRN	(1 << 2)	/* Tx/Rx NAK */
693 #define UDCCSR_PC	(1 << 1)	/* Packet Complete */
694 #define UDCCSR_FS	(1 << 0)	/* FIFO needs service */
695 
696 #define UDCBCN(x)	(0x40600200 + ((x) << 2))
697 #define UDCBCR0         0x40600200 /* Byte Count Register - EP0 */
698 #define UDCBCRA         0x40600204 /* Byte Count Register - EPA */
699 #define UDCBCRB         0x40600208 /* Byte Count Register - EPB */
700 #define UDCBCRC         0x4060020C /* Byte Count Register - EPC */
701 #define UDCBCRD         0x40600210 /* Byte Count Register - EPD */
702 #define UDCBCRE         0x40600214 /* Byte Count Register - EPE */
703 #define UDCBCRF         0x40600218 /* Byte Count Register - EPF */
704 #define UDCBCRG         0x4060021C /* Byte Count Register - EPG */
705 #define UDCBCRH         0x40600220 /* Byte Count Register - EPH */
706 #define UDCBCRI         0x40600224 /* Byte Count Register - EPI */
707 #define UDCBCRJ         0x40600228 /* Byte Count Register - EPJ */
708 #define UDCBCRK         0x4060022C /* Byte Count Register - EPK */
709 #define UDCBCRL         0x40600230 /* Byte Count Register - EPL */
710 #define UDCBCRM         0x40600234 /* Byte Count Register - EPM */
711 #define UDCBCRN         0x40600238 /* Byte Count Register - EPN */
712 #define UDCBCRP         0x4060023C /* Byte Count Register - EPP */
713 #define UDCBCRQ         0x40600240 /* Byte Count Register - EPQ */
714 #define UDCBCRR         0x40600244 /* Byte Count Register - EPR */
715 #define UDCBCRS         0x40600248 /* Byte Count Register - EPS */
716 #define UDCBCRT         0x4060024C /* Byte Count Register - EPT */
717 #define UDCBCRU         0x40600250 /* Byte Count Register - EPU */
718 #define UDCBCRV         0x40600254 /* Byte Count Register - EPV */
719 #define UDCBCRW         0x40600258 /* Byte Count Register - EPW */
720 #define UDCBCRX         0x4060025C /* Byte Count Register - EPX */
721 
722 #define UDCDN(x)	(0x40600300 + ((x) << 2))
723 #define UDCDR0          0x40600300 /* Data Register - EP0 */
724 #define UDCDRA          0x40600304 /* Data Register - EPA */
725 #define UDCDRB          0x40600308 /* Data Register - EPB */
726 #define UDCDRC          0x4060030C /* Data Register - EPC */
727 #define UDCDRD          0x40600310 /* Data Register - EPD */
728 #define UDCDRE          0x40600314 /* Data Register - EPE */
729 #define UDCDRF          0x40600318 /* Data Register - EPF */
730 #define UDCDRG          0x4060031C /* Data Register - EPG */
731 #define UDCDRH          0x40600320 /* Data Register - EPH */
732 #define UDCDRI          0x40600324 /* Data Register - EPI */
733 #define UDCDRJ          0x40600328 /* Data Register - EPJ */
734 #define UDCDRK          0x4060032C /* Data Register - EPK */
735 #define UDCDRL          0x40600330 /* Data Register - EPL */
736 #define UDCDRM          0x40600334 /* Data Register - EPM */
737 #define UDCDRN          0x40600338 /* Data Register - EPN */
738 #define UDCDRP          0x4060033C /* Data Register - EPP */
739 #define UDCDRQ          0x40600340 /* Data Register - EPQ */
740 #define UDCDRR          0x40600344 /* Data Register - EPR */
741 #define UDCDRS          0x40600348 /* Data Register - EPS */
742 #define UDCDRT          0x4060034C /* Data Register - EPT */
743 #define UDCDRU          0x40600350 /* Data Register - EPU */
744 #define UDCDRV          0x40600354 /* Data Register - EPV */
745 #define UDCDRW          0x40600358 /* Data Register - EPW */
746 #define UDCDRX          0x4060035C /* Data Register - EPX */
747 
748 #define UDCCN(x)	(0x40600400 + ((x) << 2))
749 #define UDCCRA          0x40600404 /* Configuration register EPA */
750 #define UDCCRB          0x40600408 /* Configuration register EPB */
751 #define UDCCRC          0x4060040C /* Configuration register EPC */
752 #define UDCCRD          0x40600410 /* Configuration register EPD */
753 #define UDCCRE          0x40600414 /* Configuration register EPE */
754 #define UDCCRF          0x40600418 /* Configuration register EPF */
755 #define UDCCRG          0x4060041C /* Configuration register EPG */
756 #define UDCCRH          0x40600420 /* Configuration register EPH */
757 #define UDCCRI          0x40600424 /* Configuration register EPI */
758 #define UDCCRJ          0x40600428 /* Configuration register EPJ */
759 #define UDCCRK          0x4060042C /* Configuration register EPK */
760 #define UDCCRL          0x40600430 /* Configuration register EPL */
761 #define UDCCRM          0x40600434 /* Configuration register EPM */
762 #define UDCCRN          0x40600438 /* Configuration register EPN */
763 #define UDCCRP          0x4060043C /* Configuration register EPP */
764 #define UDCCRQ          0x40600440 /* Configuration register EPQ */
765 #define UDCCRR          0x40600444 /* Configuration register EPR */
766 #define UDCCRS          0x40600448 /* Configuration register EPS */
767 #define UDCCRT          0x4060044C /* Configuration register EPT */
768 #define UDCCRU          0x40600450 /* Configuration register EPU */
769 #define UDCCRV          0x40600454 /* Configuration register EPV */
770 #define UDCCRW          0x40600458 /* Configuration register EPW */
771 #define UDCCRX          0x4060045C /* Configuration register EPX */
772 
773 #define UDCCONR_CN	(0x03 << 25)	/* Configuration Number */
774 #define UDCCONR_CN_S	(25)
775 #define UDCCONR_IN	(0x07 << 22)	/* Interface Number */
776 #define UDCCONR_IN_S	(22)
777 #define UDCCONR_AISN	(0x07 << 19)	/* Alternate Interface Number */
778 #define UDCCONR_AISN_S	(19)
779 #define UDCCONR_EN	(0x0f << 15)	/* Endpoint Number */
780 #define UDCCONR_EN_S	(15)
781 #define UDCCONR_ET	(0x03 << 13)	/* Endpoint Type: */
782 #define UDCCONR_ET_S	(13)
783 #define UDCCONR_ET_INT	(0x03 << 13)	/* Interrupt */
784 #define UDCCONR_ET_BULK	(0x02 << 13)	/* Bulk */
785 #define UDCCONR_ET_ISO	(0x01 << 13)	/* Isochronous */
786 #define UDCCONR_ET_NU	(0x00 << 13)	/* Not used */
787 #define UDCCONR_ED	(1 << 12)	/* Endpoint Direction */
788 #define UDCCONR_MPS	(0x3ff << 2)	/* Maximum Packet Size */
789 #define UDCCONR_MPS_S	(2)
790 #define UDCCONR_DE	(1 << 1)	/* Double Buffering Enable */
791 #define UDCCONR_EE	(1 << 0)	/* Endpoint Enable */
792 
793 
794 #define UDC_INT_FIFOERROR	(0x2)
795 #define UDC_INT_PACKETCMP	(0x1)
796 #define UDC_FNR_MASK		(0x7ff)
797 #define UDCCSR_WR_MASK		(UDCCSR_DME|UDCCSR_FST)
798 #define UDC_BCR_MASK		(0x3ff)
799 
800 #endif /* CONFIG_CPU_PXA27X */
801 
802 #if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
803 
804 /******************************************************************************/
805 /*
806  * USB Host Controller
807  */
808 #define OHCI_REGS_BASE	0x4C000000	/* required for ohci driver */
809 #define UHCREV		0x4C000000
810 #define UHCHCON		0x4C000004
811 #define UHCCOMS		0x4C000008
812 #define UHCINTS		0x4C00000C
813 #define UHCINTE		0x4C000010
814 #define UHCINTD		0x4C000014
815 #define UHCHCCA		0x4C000018
816 #define UHCPCED		0x4C00001C
817 #define UHCCHED		0x4C000020
818 #define UHCCCED		0x4C000024
819 #define UHCBHED		0x4C000028
820 #define UHCBCED		0x4C00002C
821 #define UHCDHEAD	0x4C000030
822 #define UHCFMI		0x4C000034
823 #define UHCFMR		0x4C000038
824 #define UHCFMN		0x4C00003C
825 #define UHCPERS		0x4C000040
826 #define UHCLST		0x4C000044
827 #define UHCRHDA		0x4C000048
828 #define UHCRHDB		0x4C00004C
829 #define UHCRHS		0x4C000050
830 #define UHCRHPS1	0x4C000054
831 #define UHCRHPS2	0x4C000058
832 #define UHCRHPS3	0x4C00005C
833 #define UHCSTAT		0x4C000060
834 #define UHCHR		0x4C000064
835 #define UHCHIE		0x4C000068
836 #define UHCHIT		0x4C00006C
837 
838 #define UHCCOMS_HCR	(1<<0)
839 
840 #define UHCHR_FSBIR	(1<<0)
841 #define UHCHR_FHR	(1<<1)
842 #define UHCHR_CGR	(1<<2)
843 #define UHCHR_SSDC	(1<<3)
844 #define UHCHR_UIT	(1<<4)
845 #define UHCHR_SSE	(1<<5)
846 #define UHCHR_PSPL	(1<<6)
847 #define UHCHR_PCPL	(1<<7)
848 #define UHCHR_SSEP0	(1<<9)
849 #define UHCHR_SSEP1	(1<<10)
850 #define UHCHR_SSEP2	(1<<11)
851 
852 #define UHCHIE_UPRIE	(1<<13)
853 #define UHCHIE_UPS2IE	(1<<12)
854 #define UHCHIE_UPS1IE	(1<<11)
855 #define UHCHIE_TAIE	(1<<10)
856 #define UHCHIE_HBAIE	(1<<8)
857 #define UHCHIE_RWIE	(1<<7)
858 
859 #define UP2OCR		0x40600020
860 
861 #define UP2OCR_HXOE	(1<<17)
862 #define UP2OCR_HXS	(1<<16)
863 #define UP2OCR_IDON	(1<<10)
864 #define UP2OCR_EXSUS	(1<<9)
865 #define UP2OCR_EXSP	(1<<8)
866 #define UP2OCR_DMSTATE	(1<<7)
867 #define UP2OCR_VPM	(1<<6)
868 #define UP2OCR_DPSTATE	(1<<5)
869 #define UP2OCR_DPPUE	(1<<4)
870 #define UP2OCR_DMPDE	(1<<3)
871 #define UP2OCR_DPPDE	(1<<2)
872 #define UP2OCR_CPVPE	(1<<1)
873 #define UP2OCR_CPVEN	(1<<0)
874 
875 #endif	/* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */
876 
877 /******************************************************************************/
878 /*
879  * Fast Infrared Communication Port
880  */
881 #define ICCR0		0x40800000  /* ICP Control Register 0 */
882 #define ICCR1		0x40800004  /* ICP Control Register 1 */
883 #define ICCR2		0x40800008  /* ICP Control Register 2 */
884 #define ICDR		0x4080000c  /* ICP Data Register */
885 #define ICSR0		0x40800014  /* ICP Status Register 0 */
886 #define ICSR1		0x40800018  /* ICP Status Register 1 */
887 
888 /*
889  * Real Time Clock
890  */
891 #define RCNR		0x40900000  /* RTC Count Register */
892 #define RTAR		0x40900004  /* RTC Alarm Register */
893 #define RTSR		0x40900008  /* RTC Status Register */
894 #define RTTR		0x4090000C  /* RTC Timer Trim Register */
895 #define RDAR1		0x40900018  /* Wristwatch Day Alarm Reg 1 */
896 #define RDAR2		0x40900020  /* Wristwatch Day Alarm Reg 2 */
897 #define RYAR1		0x4090001C  /* Wristwatch Year Alarm Reg 1 */
898 #define RYAR2		0x40900024  /* Wristwatch Year Alarm Reg 2 */
899 #define SWAR1		0x4090002C  /* Stopwatch Alarm Register 1 */
900 #define SWAR2		0x40900030  /* Stopwatch Alarm Register 2 */
901 #define PIAR		0x40900038  /* Periodic Interrupt Alarm Register */
902 #define RDCR		0x40900010  /* RTC Day Count Register. */
903 #define RYCR		0x40900014  /* RTC Year Count Register. */
904 #define SWCR		0x40900028  /* Stopwatch Count Register */
905 #define RTCPICR		0x40900034  /* Periodic Interrupt Counter Register */
906 
907 #define RTSR_PICE	(1 << 15)	/* Peridoc interrupt count enable */
908 #define RTSR_PIALE	(1 << 14)	/* Peridoc interrupt Alarm enable */
909 #define RTSR_PIAL	(1 << 13)	/* Peridoc  interrupt Alarm status */
910 #define RTSR_HZE	(1 << 3)	/* HZ interrupt enable */
911 #define RTSR_ALE	(1 << 2)	/* RTC alarm interrupt enable */
912 #define RTSR_HZ		(1 << 1)	/* HZ rising-edge detected */
913 #define RTSR_AL		(1 << 0)	/* RTC alarm detected */
914 
915 /******************************************************************************/
916 /*
917  * OS Timer & Match Registers
918  */
919 #define OSMR0		0x40A00000  /* OS Timer Match Register 0 */
920 #define OSMR1		0x40A00004  /* OS Timer Match Register 1 */
921 #define OSMR2		0x40A00008  /* OS Timer Match Register 2 */
922 #define OSMR3		0x40A0000C  /* OS Timer Match Register 3 */
923 #define OSCR		0x40A00010  /* OS Timer Counter Register */
924 #define OSSR		0x40A00014  /* OS Timer Status Register */
925 #define OWER		0x40A00018  /* OS Timer Watchdog Enable Register */
926 #define OIER		0x40A0001C  /* OS Timer Interrupt Enable Register */
927 
928 #if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
929 #define OSCR4		0x40A00040  /* OS Timer Counter Register 4 */
930 #define OSCR5		0x40A00044  /* OS Timer Counter Register 5 */
931 #define OSCR6		0x40A00048  /* OS Timer Counter Register 6 */
932 #define OSCR7		0x40A0004C  /* OS Timer Counter Register 7 */
933 #define OSCR8		0x40A00050  /* OS Timer Counter Register 8 */
934 #define OSCR9		0x40A00054  /* OS Timer Counter Register 9 */
935 #define OSCR10		0x40A00058  /* OS Timer Counter Register 10 */
936 #define OSCR11		0x40A0005C  /* OS Timer Counter Register 11 */
937 
938 #define OSMR4		0x40A00080  /* OS Timer Match Register 4 */
939 #define OSMR5		0x40A00084  /* OS Timer Match Register 5 */
940 #define OSMR6		0x40A00088  /* OS Timer Match Register 6 */
941 #define OSMR7		0x40A0008C  /* OS Timer Match Register 7 */
942 #define OSMR8		0x40A00090  /* OS Timer Match Register 8 */
943 #define OSMR9		0x40A00094  /* OS Timer Match Register 9 */
944 #define OSMR10		0x40A00098  /* OS Timer Match Register 10 */
945 #define OSMR11		0x40A0009C  /* OS Timer Match Register 11 */
946 
947 #define OMCR4		0x40A000C0  /* OS Match Control Register 4 */
948 #define OMCR5		0x40A000C4  /* OS Match Control Register 5 */
949 #define OMCR6		0x40A000C8  /* OS Match Control Register 6 */
950 #define OMCR7		0x40A000CC  /* OS Match Control Register 7 */
951 #define OMCR8		0x40A000D0  /* OS Match Control Register 8 */
952 #define OMCR9		0x40A000D4  /* OS Match Control Register 9 */
953 #define OMCR10		0x40A000D8  /* OS Match Control Register 10 */
954 #define OMCR11		0x40A000DC  /* OS Match Control Register 11 */
955 
956 #endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */
957 
958 #define OSSR_M4		(1 << 4)	/* Match status channel 4 */
959 #define OSSR_M3		(1 << 3)	/* Match status channel 3 */
960 #define OSSR_M2		(1 << 2)	/* Match status channel 2 */
961 #define OSSR_M1		(1 << 1)	/* Match status channel 1 */
962 #define OSSR_M0		(1 << 0)	/* Match status channel 0 */
963 
964 #define OWER_WME	(1 << 0)	/* Watchdog Match Enable */
965 
966 #define OIER_E4		(1 << 4)	/* Interrupt enable channel 4 */
967 #define OIER_E3		(1 << 3)	/* Interrupt enable channel 3 */
968 #define OIER_E2		(1 << 2)	/* Interrupt enable channel 2 */
969 #define OIER_E1		(1 << 1)	/* Interrupt enable channel 1 */
970 #define OIER_E0		(1 << 0)	/* Interrupt enable channel 0 */
971 
972 #define	OSCR_CLK_FREQ	3250
973 
974 /******************************************************************************/
975 /*
976  * Core Clock
977  */
978 
979 #if defined(CONFIG_CPU_MONAHANS)
980 #define ACCR		0x41340000  /* Application Subsystem Clock Configuration Register */
981 #define ACSR		0x41340004  /* Application Subsystem Clock Status Register */
982 #define AICSR		0x41340008  /* Application Subsystem Interrupt Control/Status Register */
983 #define CKENA		0x4134000C  /* A Clock Enable Register */
984 #define CKENB		0x41340010  /* B Clock Enable Register */
985 #define AC97_DIV	0x41340014  /* AC97 clock divisor value register */
986 
987 #define ACCR_SMC_MASK	0x03800000	/* Static Memory Controller Frequency Select */
988 #define ACCR_SRAM_MASK	0x000c0000	/* SRAM Controller Frequency Select */
989 #define ACCR_FC_MASK	0x00030000	/* Frequency Change Frequency Select */
990 #define ACCR_HSIO_MASK	0x0000c000	/* High Speed IO Frequency Select */
991 #define ACCR_DDR_MASK	0x00003000	/* DDR Memory Controller Frequency Select */
992 #define ACCR_XN_MASK	0x00000700	/* Run Mode Frequency to Turbo Mode Frequency Multiplier */
993 #define ACCR_XL_MASK	0x0000001f	/* Crystal Frequency to Memory Frequency Multiplier */
994 #define ACCR_XPDIS	(1 << 31)
995 #define ACCR_SPDIS	(1 << 30)
996 #define ACCR_13MEND1	(1 << 27)
997 #define ACCR_D0CS	(1 << 26)
998 #define ACCR_13MEND2	(1 << 21)
999 #define ACCR_PCCE	(1 << 11)
1000 
1001 #define CKENA_30_MSL0	(1 << 30)	/* MSL0 Interface Unit Clock Enable */
1002 #define CKENA_29_SSP4	(1 << 29)	/* SSP3 Unit Clock Enable */
1003 #define CKENA_28_SSP3	(1 << 28)	/* SSP2 Unit Clock Enable */
1004 #define CKENA_27_SSP2	(1 << 27)	/* SSP1 Unit Clock Enable */
1005 #define CKENA_26_SSP1	(1 << 26)	/* SSP0 Unit Clock Enable */
1006 #define CKENA_25_TSI	(1 << 25)	/* TSI Clock Enable */
1007 #define CKENA_24_AC97	(1 << 24)	/* AC97 Unit Clock Enable */
1008 #define CKENA_23_STUART	(1 << 23)	/* STUART Unit Clock Enable */
1009 #define CKENA_22_FFUART	(1 << 22)	/* FFUART Unit Clock Enable */
1010 #define CKENA_21_BTUART	(1 << 21)	/* BTUART Unit Clock Enable */
1011 #define CKENA_20_UDC	(1 << 20)	/* UDC Clock Enable */
1012 #define CKENA_19_TPM	(1 << 19)	/* TPM Unit Clock Enable */
1013 #define CKENA_18_USIM1	(1 << 18)	/* USIM1 Unit Clock Enable */
1014 #define CKENA_17_USIM0	(1 << 17)	/* USIM0 Unit Clock Enable */
1015 #define CKENA_15_CIR	(1 << 15)	/* Consumer IR Clock Enable */
1016 #define CKENA_14_KEY	(1 << 14)	/* Keypad Controller Clock Enable */
1017 #define CKENA_13_MMC1	(1 << 13)	/* MMC1 Clock Enable */
1018 #define CKENA_12_MMC0	(1 << 12)	/* MMC0 Clock Enable */
1019 #define CKENA_11_FLASH	(1 << 11)	/* Boot ROM Clock Enable */
1020 #define CKENA_10_SRAM	(1 << 10)	/* SRAM Controller Clock Enable */
1021 #define CKENA_9_SMC	(1 << 9)	/* Static Memory Controller */
1022 #define CKENA_8_DMC	(1 << 8)	/* Dynamic Memory Controller */
1023 #define CKENA_7_GRAPHICS (1 << 7)	/* 2D Graphics Clock Enable */
1024 #define CKENA_6_USBCLI	(1 << 6)	/* USB Client Unit Clock Enable */
1025 #define CKENA_4_NAND	(1 << 4)	/* NAND Flash Controller Clock Enable */
1026 #define CKENA_3_CAMERA	(1 << 3)	/* Camera Interface Clock Enable */
1027 #define CKENA_2_USBHOST	(1 << 2)	/* USB Host Unit Clock Enable */
1028 #define CKENA_1_LCD	(1 << 1)	/* LCD Unit Clock Enable */
1029 
1030 #define CKENB_9_SYSBUS2	(1 << 9)	/* System bus 2 */
1031 #define CKENB_8_1WIRE	(1 << 8)	/* One Wire Interface Unit Clock Enable */
1032 #define CKENB_7_GPIO	(1 << 7)	/* GPIO Clock Enable */
1033 #define CKENB_6_IRQ	(1 << 6)	/* Interrupt Controller Clock Enable */
1034 #define CKENB_4_I2C	(1 << 4)	/* I2C Unit Clock Enable */
1035 #define CKENB_1_PWM1	(1 << 1)	/* PWM2 & PWM3 Clock Enable */
1036 #define CKENB_0_PWM0	(1 << 0)	/* PWM0 & PWM1 Clock Enable */
1037 
1038 #else /* if defined CONFIG_CPU_MONAHANS */
1039 
1040 #define CCCR		0x41300000  /* Core Clock Configuration Register */
1041 #define CKEN		0x41300004  /* Clock Enable Register */
1042 #define OSCC		0x41300008  /* Oscillator Configuration Register */
1043 #define CCSR		0x4130000C /* Core Clock Status Register */
1044 
1045 #define CKEN23_SSP1	(1 << 23) /* SSP1 Unit Clock Enable */
1046 #define CKEN22_MEMC	(1 << 22) /* Memory Controler */
1047 #define CKEN21_MSHC	(1 << 21) /* Memery Stick Host Controller */
1048 #define CKEN20_IM	(1 << 20) /* Internal Memory Clock Enable */
1049 #define CKEN19_KEYPAD	(1 << 19) /* Keypad Interface Clock Enable */
1050 #define CKEN18_USIM	(1 << 18) /* USIM Unit Clock Enable */
1051 #define CKEN17_MSL	(1 << 17) /* MSL Interface Unit Clock Enable */
1052 #define CKEN15_PWR_I2C	(1 << 15) /* PWR_I2C Unit Clock Enable */
1053 #define CKEN9_OST	(1 << 9)  /* OS Timer Unit Clock Enable */
1054 #define CKEN4_SSP3	(1 << 4)  /* SSP3 Unit Clock Enable */
1055 
1056 #define CCCR_N_MASK	0x0380		/* Run Mode Frequency to Turbo Mode Frequency Multiplier */
1057 #if !defined(CONFIG_CPU_PXA27X)
1058 #define CCCR_M_MASK	0x0060		/* Memory Frequency to Run Mode Frequency Multiplier */
1059 #endif
1060 #define CCCR_L_MASK	0x001f		/* Crystal Frequency to Memory Frequency Multiplier */
1061 
1062 #define CKEN24_CAMERA	(1 << 24)	/* Camera Interface Clock Enable */
1063 #define CKEN23_SSP1	(1 << 23)	/* SSP1 Unit Clock Enable */
1064 #define CKEN22_MEMC	(1 << 22)	/* Memory Controller Clock Enable */
1065 #define CKEN21_MEMSTK	(1 << 21)	/* Memory Stick Host Controller */
1066 #define CKEN20_IM	(1 << 20)	/* Internal Memory Clock Enable */
1067 #define CKEN19_KEYPAD	(1 << 19)	/* Keypad Interface Clock Enable */
1068 #define CKEN18_USIM	(1 << 18)	/* USIM Unit Clock Enable */
1069 #define CKEN17_MSL	(1 << 17)	/* MSL Unit Clock Enable */
1070 #define CKEN16_LCD	(1 << 16)	/* LCD Unit Clock Enable */
1071 #define CKEN15_PWRI2C	(1 << 15)	/* PWR I2C Unit Clock Enable */
1072 #define CKEN14_I2C	(1 << 14)	/* I2C Unit Clock Enable */
1073 #define CKEN13_FICP	(1 << 13)	/* FICP Unit Clock Enable */
1074 #define CKEN12_MMC	(1 << 12)	/* MMC Unit Clock Enable */
1075 #define CKEN11_USB	(1 << 11)	/* USB Unit Clock Enable */
1076 #if defined(CONFIG_CPU_PXA27X)
1077 #define CKEN10_USBHOST	(1 << 10)	/* USB Host Unit Clock Enable */
1078 #define CKEN24_CAMERA	(1 << 24)	/* Camera Unit Clock Enable */
1079 #endif
1080 #define CKEN8_I2S	(1 << 8)	/* I2S Unit Clock Enable */
1081 #define CKEN7_BTUART	(1 << 7)	/* BTUART Unit Clock Enable */
1082 #define CKEN6_FFUART	(1 << 6)	/* FFUART Unit Clock Enable */
1083 #define CKEN5_STUART	(1 << 5)	/* STUART Unit Clock Enable */
1084 #define CKEN3_SSP	(1 << 3)	/* SSP Unit Clock Enable */
1085 #define CKEN2_AC97	(1 << 2)	/* AC97 Unit Clock Enable */
1086 #define CKEN1_PWM1	(1 << 1)	/* PWM1 Clock Enable */
1087 #define CKEN0_PWM0	(1 << 0)	/* PWM0 Clock Enable */
1088 
1089 #define OSCC_OON	(1 << 1)	/* 32.768kHz OON (write-once only bit) */
1090 #define OSCC_OOK	(1 << 0)	/* 32.768kHz OOK (read-only bit) */
1091 
1092 #if !defined(CONFIG_CPU_PXA27X)
1093 #define	 CCCR_L09      (0x1F)
1094 #define	 CCCR_L27      (0x1)
1095 #define	 CCCR_L32      (0x2)
1096 #define	 CCCR_L36      (0x3)
1097 #define	 CCCR_L40      (0x4)
1098 #define	 CCCR_L45      (0x5)
1099 
1100 #define	 CCCR_M1       (0x1 << 5)
1101 #define	 CCCR_M2       (0x2 << 5)
1102 #define	 CCCR_M4       (0x3 << 5)
1103 
1104 #define	 CCCR_N10      (0x2 << 7)
1105 #define	 CCCR_N15      (0x3 << 7)
1106 #define	 CCCR_N20      (0x4 << 7)
1107 #define	 CCCR_N25      (0x5 << 7)
1108 #define	 CCCR_N30      (0x6 << 7)
1109 #endif
1110 
1111 #endif /* CONFIG_CPU_MONAHANS */
1112 
1113 /******************************************************************************/
1114 /*
1115  * Pulse Width Modulator
1116  */
1117 #define PWM_CTRL0	0x40B00000  /* PWM 0 Control Register */
1118 #define PWM_PWDUTY0	0x40B00004  /* PWM 0 Duty Cycle Register */
1119 #define PWM_PERVAL0	0x40B00008  /* PWM 0 Period Control Register */
1120 
1121 #define PWM_CTRL1	0x40C00000  /* PWM 1 Control Register */
1122 #define PWM_PWDUTY1	0x40C00004  /* PWM 1 Duty Cycle Register */
1123 #define PWM_PERVAL1	0x40C00008  /* PWM 1 Period Control Register */
1124 
1125 #if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
1126 #define PWM_CTRL2	0x40B00010  /* PWM 2 Control Register */
1127 #define PWM_PWDUTY2	0x40B00014  /* PWM 2 Duty Cycle Register */
1128 #define PWM_PERVAL2	0x40B00018  /* PWM 2 Period Control Register */
1129 
1130 #define PWM_CTRL3	0x40C00010  /* PWM 3 Control Register */
1131 #define PWM_PWDUTY3	0x40C00014  /* PWM 3 Duty Cycle Register */
1132 #define PWM_PERVAL3	0x40C00018  /* PWM 3 Period Control Register */
1133 #endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */
1134 
1135 /*
1136  * Interrupt Controller
1137  */
1138 #define ICIP		0x40D00000  /* Interrupt Controller IRQ Pending Register */
1139 #define ICMR		0x40D00004  /* Interrupt Controller Mask Register */
1140 #define ICLR		0x40D00008  /* Interrupt Controller Level Register */
1141 #define ICFP		0x40D0000C  /* Interrupt Controller FIQ Pending Register */
1142 #define ICPR		0x40D00010  /* Interrupt Controller Pending Register */
1143 #define ICCR		0x40D00014  /* Interrupt Controller Control Register */
1144 
1145 #if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
1146 #define ICHP		0x40D00018  /* Interrupt Controller Highest Priority Register */
1147 #define ICIP2		0x40D0009C  /* Interrupt Controller IRQ Pending Register 2 */
1148 #define ICMR2		0x40D000A0  /* Interrupt Controller Mask Register 2 */
1149 #define ICLR2		0x40D000A4  /* Interrupt Controller Level Register 2 */
1150 #define ICFP2		0x40D000A8  /* Interrupt Controller FIQ Pending Register 2 */
1151 #define ICPR2		0x40D000AC  /* Interrupt Controller Pending Register 2 */
1152 #endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */
1153 
1154 /******************************************************************************/
1155 /*
1156  * General Purpose I/O
1157  */
1158 #define GPLR0		0x40E00000  /* GPIO Pin-Level Register GPIO<31:0> */
1159 #define GPLR1		0x40E00004  /* GPIO Pin-Level Register GPIO<63:32> */
1160 #define GPLR2		0x40E00008  /* GPIO Pin-Level Register GPIO<80:64> */
1161 
1162 #define GPDR0		0x40E0000C  /* GPIO Pin Direction Register GPIO<31:0> */
1163 #define GPDR1		0x40E00010  /* GPIO Pin Direction Register GPIO<63:32> */
1164 #define GPDR2		0x40E00014  /* GPIO Pin Direction Register GPIO<80:64> */
1165 
1166 #define GPSR0		0x40E00018  /* GPIO Pin Output Set Register GPIO<31:0> */
1167 #define GPSR1		0x40E0001C  /* GPIO Pin Output Set Register GPIO<63:32> */
1168 #define GPSR2		0x40E00020  /* GPIO Pin Output Set Register GPIO<80:64> */
1169 
1170 #define GPCR0		0x40E00024  /* GPIO Pin Output Clear Register GPIO<31:0> */
1171 #define GPCR1		0x40E00028  /* GPIO Pin Output Clear Register GPIO <63:32> */
1172 #define GPCR2		0x40E0002C  /* GPIO Pin Output Clear Register GPIO <80:64> */
1173 
1174 #define GRER0		0x40E00030  /* GPIO Rising-Edge Detect Register GPIO<31:0> */
1175 #define GRER1		0x40E00034  /* GPIO Rising-Edge Detect Register GPIO<63:32> */
1176 #define GRER2		0x40E00038  /* GPIO Rising-Edge Detect Register GPIO<80:64> */
1177 
1178 #define GFER0		0x40E0003C  /* GPIO Falling-Edge Detect Register GPIO<31:0> */
1179 #define GFER1		0x40E00040  /* GPIO Falling-Edge Detect Register GPIO<63:32> */
1180 #define GFER2		0x40E00044  /* GPIO Falling-Edge Detect Register GPIO<80:64> */
1181 
1182 #define GEDR0		0x40E00048  /* GPIO Edge Detect Status Register GPIO<31:0> */
1183 #define GEDR1		0x40E0004C  /* GPIO Edge Detect Status Register GPIO<63:32> */
1184 #define GEDR2		0x40E00050  /* GPIO Edge Detect Status Register GPIO<80:64> */
1185 
1186 #define GAFR0_L		0x40E00054  /* GPIO Alternate Function Select Register GPIO<15:0> */
1187 #define GAFR0_U		0x40E00058  /* GPIO Alternate Function Select Register GPIO<31:16> */
1188 #define GAFR1_L		0x40E0005C  /* GPIO Alternate Function Select Register GPIO<47:32> */
1189 #define GAFR1_U		0x40E00060  /* GPIO Alternate Function Select Register GPIO<63:48> */
1190 #define GAFR2_L		0x40E00064  /* GPIO Alternate Function Select Register GPIO<79:64> */
1191 #define GAFR2_U		0x40E00068  /* GPIO Alternate Function Select Register GPIO 80 */
1192 
1193 #if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
1194 #define GPLR3		0x40E00100  /* GPIO Pin-Level Register GPIO<127:96> */
1195 #define GPDR3		0x40E0010C  /* GPIO Pin Direction Register GPIO<127:96> */
1196 #define GPSR3		0x40E00118  /* GPIO Pin Output Set Register GPIO<127:96> */
1197 #define GPCR3		0x40E00124  /* GPIO Pin Output Clear Register GPIO<127:96> */
1198 #define GRER3		0x40E00130  /* GPIO Rising-Edge Detect Register GPIO<127:96> */
1199 #define GFER3		0x40E0013C  /* GPIO Falling-Edge Detect Register GPIO<127:96> */
1200 #define GEDR3		0x40E00148  /* GPIO Edge Detect Status Register GPIO<127:96> */
1201 #define GAFR3_L		0x40E0006C  /* GPIO Alternate Function Select Register GPIO<111:96> */
1202 #define GAFR3_U		0x40E00070  /* GPIO Alternate Function Select Register GPIO<127:112> */
1203 #endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */
1204 
1205 #ifdef CONFIG_CPU_MONAHANS
1206 #define GSDR0		0x40E00400 /* Bit-wise Set of GPDR[31:0] */
1207 #define GSDR1		0x40E00404 /* Bit-wise Set of GPDR[63:32] */
1208 #define GSDR2		0x40E00408 /* Bit-wise Set of GPDR[95:64] */
1209 #define GSDR3		0x40E0040C /* Bit-wise Set of GPDR[127:96] */
1210 
1211 #define GCDR0		0x40E00420 /* Bit-wise Clear of GPDR[31:0] */
1212 #define GCDR1		0x40E00424 /* Bit-wise Clear of GPDR[63:32] */
1213 #define GCDR2		0x40E00428 /* Bit-wise Clear of GPDR[95:64] */
1214 #define GCDR3		0x40E0042C /* Bit-wise Clear of GPDR[127:96] */
1215 
1216 #define GSRER0		0x40E00440 /* Set Rising Edge Det. Enable [31:0] */
1217 #define GSRER1		0x40E00444 /* Set Rising Edge Det. Enable [63:32] */
1218 #define GSRER2		0x40E00448 /* Set Rising Edge Det. Enable [95:64] */
1219 #define GSRER3		0x40E0044C /* Set Rising Edge Det. Enable [127:96] */
1220 
1221 #define GCRER0		0x40E00460 /* Clear Rising Edge Det. Enable [31:0] */
1222 #define GCRER1		0x40E00464 /* Clear Rising Edge Det. Enable [63:32] */
1223 #define GCRER2		0x40E00468 /* Clear Rising Edge Det. Enable [95:64] */
1224 #define GCRER3		0x40E0046C /* Clear Rising Edge Det. Enable[127:96] */
1225 
1226 #define GSFER0		0x40E00480 /* Set Falling Edge Det. Enable [31:0] */
1227 #define GSFER1		0x40E00484 /* Set Falling Edge Det. Enable [63:32] */
1228 #define GSFER2		0x40E00488 /* Set Falling Edge Det. Enable [95:64] */
1229 #define GSFER3		0x40E0048C /* Set Falling Edge Det. Enable[127:96] */
1230 
1231 #define GCFER0		0x40E004A0 /* Clr Falling Edge Det. Enable [31:0] */
1232 #define GCFER1		0x40E004A4 /* Clr Falling Edge Det. Enable [63:32] */
1233 #define GCFER2		0x40E004A8 /* Clr Falling Edge Det. Enable [95:64] */
1234 #define GCFER3		0x40E004AC /* Clr Falling Edge Det. Enable[127:96] */
1235 
1236 #define GSDR(x)		(0x40E00400 | ((x) & 0x60) >> 3)
1237 #define GCDR(x)		(0x40E00420 | ((x) & 0x60) >> 3)
1238 #endif
1239 
1240 #define _GPLR(x)	(0x40E00000 + (((x) & 0x60) >> 3))
1241 #define _GPDR(x)	(0x40E0000C + (((x) & 0x60) >> 3))
1242 #define _GPSR(x)	(0x40E00018 + (((x) & 0x60) >> 3))
1243 #define _GPCR(x)	(0x40E00024 + (((x) & 0x60) >> 3))
1244 #define _GRER(x)	(0x40E00030 + (((x) & 0x60) >> 3))
1245 #define _GFER(x)	(0x40E0003C + (((x) & 0x60) >> 3))
1246 #define _GEDR(x)	(0x40E00048 + (((x) & 0x60) >> 3))
1247 #define _GAFR(x)	(0x40E00054 + (((x) & 0x70) >> 2))
1248 
1249 #if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
1250 #define GPLR(x)		(((((x) & 0x7f) < 96) ? _GPLR(x) : GPLR3))
1251 #define GPDR(x)		(((((x) & 0x7f) < 96) ? _GPDR(x) : GPDR3))
1252 #define GPSR(x)		(((((x) & 0x7f) < 96) ? _GPSR(x) : GPSR3))
1253 #define GPCR(x)		(((((x) & 0x7f) < 96) ? _GPCR(x) : GPCR3))
1254 #define GRER(x)		(((((x) & 0x7f) < 96) ? _GRER(x) : GRER3))
1255 #define GFER(x)		(((((x) & 0x7f) < 96) ? _GFER(x) : GFER3))
1256 #define GEDR(x)		(((((x) & 0x7f) < 96) ? _GEDR(x) : GEDR3))
1257 #define GAFR(x)		(((((x) & 0x7f) < 96) ? _GAFR(x) : \
1258 			((((x) & 0x7f) < 112) ? GAFR3_L : GAFR3_U)))
1259 #else
1260 #define GPLR(x)		_GPLR(x)
1261 #define GPDR(x)		_GPDR(x)
1262 #define GPSR(x)		_GPSR(x)
1263 #define GPCR(x)		_GPCR(x)
1264 #define GRER(x)		_GRER(x)
1265 #define GFER(x)		_GFER(x)
1266 #define GEDR(x)		_GEDR(x)
1267 #define GAFR(x)		_GAFR(x)
1268 #endif
1269 
1270 #define GPIO_bit(x)	(1 << ((x) & 0x1f))
1271 
1272 /******************************************************************************/
1273 /*
1274  * Multi-function Pin Registers:
1275  */
1276 /* PXA320 */
1277 #if defined(CONFIG_CPU_PXA320)
1278 #define	DF_IO0		0x40e1024c
1279 #define	DF_IO1		0x40e10254
1280 #define	DF_IO2		0x40e1025c
1281 #define	DF_IO3		0x40e10264
1282 #define	DF_IO4		0x40e1026c
1283 #define	DF_IO5		0x40e10274
1284 #define	DF_IO6		0x40e1027c
1285 #define	DF_IO7		0x40e10284
1286 #define	DF_IO8		0x40e10250
1287 #define	DF_IO9		0x40e10258
1288 #define	DF_IO10		0x40e10260
1289 #define	DF_IO11		0x40e10268
1290 #define	DF_IO12		0x40e10270
1291 #define	DF_IO13		0x40e10278
1292 #define	DF_IO14		0x40e10280
1293 #define	DF_IO15		0x40e10288
1294 #define	DF_CLE_nOE	0x40e10204
1295 #define	DF_ALE_nWE1	0x40e10208
1296 #define	DF_ALE_nWE2	0x40e1021c
1297 #define	DF_SCLK_E	0x40e10210
1298 #define	DF_nCS0		0x40e10224
1299 #define	DF_nCS1		0x40e10228
1300 #define	nBE0		0x40e10214
1301 #define	nBE1		0x40e10218
1302 #define	nLUA		0x40e10234
1303 #define	nLLA		0x40e10238
1304 #define	DF_ADDR0	0x40e1023c
1305 #define	DF_ADDR1	0x40e10240
1306 #define	DF_ADDR2	0x40e10244
1307 #define	DF_ADDR3	0x40e10248
1308 #define	DF_INT_RnB	0x40e10220
1309 #define	DF_nCS0		0x40e10224
1310 #define	DF_nCS1		0x40e10228
1311 #define	DF_nWE		0x40e1022c
1312 #define	DF_nRE		0x40e10230
1313 
1314 #define	nXCVREN		0x40e10138
1315 
1316 #define	GPIO0		0x40e10124
1317 #define	GPIO1		0x40e10128
1318 #define	GPIO2		0x40e1012c
1319 #define	GPIO3		0x40e10130
1320 #define	GPIO4		0x40e10134
1321 #define	GPIO5		0x40e1028c
1322 #define	GPIO6		0x40e10290
1323 #define	GPIO7		0x40e10294
1324 #define	GPIO8		0x40e10298
1325 #define	GPIO9		0x40e1029c
1326 #define	GPIO10		0x40e10458
1327 #define	GPIO11		0x40e102a0
1328 #define	GPIO12		0x40e102a4
1329 #define	GPIO13		0x40e102a8
1330 #define	GPIO14		0x40e102ac
1331 #define	GPIO15		0x40e102b0
1332 #define	GPIO16		0x40e102b4
1333 #define	GPIO17		0x40e102b8
1334 #define	GPIO18		0x40e102bc
1335 #define	GPIO19		0x40e102c0
1336 #define	GPIO20		0x40e102c4
1337 #define	GPIO21		0x40e102c8
1338 #define	GPIO22		0x40e102cc
1339 #define	GPIO23		0x40e102d0
1340 #define	GPIO24		0x40e102d4
1341 #define	GPIO25		0x40e102d8
1342 #define	GPIO26		0x40e102dc
1343 
1344 #define	GPIO27		0x40e10400
1345 #define	GPIO28		0x40e10404
1346 #define	GPIO29		0x40e10408
1347 #define	GPIO30		0x40e1040c
1348 #define	GPIO31		0x40e10410
1349 #define	GPIO32		0x40e10414
1350 #define	GPIO33		0x40e10418
1351 #define	GPIO34		0x40e1041c
1352 #define	GPIO35		0x40e10420
1353 #define	GPIO36		0x40e10424
1354 #define	GPIO37		0x40e10428
1355 #define	GPIO38		0x40e1042c
1356 #define	GPIO39		0x40e10430
1357 #define	GPIO40		0x40e10434
1358 #define	GPIO41		0x40e10438
1359 #define	GPIO42		0x40e1043c
1360 #define	GPIO43		0x40e10440
1361 #define	GPIO44		0x40e10444
1362 #define	GPIO45		0x40e10448
1363 #define	GPIO46		0x40e1044c
1364 #define	GPIO47		0x40e10450
1365 #define	GPIO48		0x40e10454
1366 #define	GPIO49		0x40e1045c
1367 #define	GPIO50		0x40e10460
1368 #define	GPIO51		0x40e10464
1369 #define	GPIO52		0x40e10468
1370 #define	GPIO53		0x40e1046c
1371 #define	GPIO54		0x40e10470
1372 #define	GPIO55		0x40e10474
1373 #define	GPIO56		0x40e10478
1374 #define	GPIO57		0x40e1047c
1375 #define	GPIO58		0x40e10480
1376 #define	GPIO59		0x40e10484
1377 #define	GPIO60		0x40e10488
1378 #define	GPIO61		0x40e1048c
1379 #define	GPIO62		0x40e10490
1380 
1381 #define	GPIO6_2		0x40e10494
1382 #define	GPIO7_2		0x40e10498
1383 #define	GPIO8_2		0x40e1049c
1384 #define	GPIO9_2		0x40e104a0
1385 #define	GPIO10_2	0x40e104a4
1386 #define	GPIO11_2	0x40e104a8
1387 #define	GPIO12_2	0x40e104ac
1388 #define	GPIO13_2	0x40e104b0
1389 
1390 #define	GPIO63		0x40e104b4
1391 #define	GPIO64		0x40e104b8
1392 #define	GPIO65		0x40e104bc
1393 #define	GPIO66		0x40e104c0
1394 #define	GPIO67		0x40e104c4
1395 #define	GPIO68		0x40e104c8
1396 #define	GPIO69		0x40e104cc
1397 #define	GPIO70		0x40e104d0
1398 #define	GPIO71		0x40e104d4
1399 #define	GPIO72		0x40e104d8
1400 #define	GPIO73		0x40e104dc
1401 
1402 #define	GPIO14_2	0x40e104e0
1403 #define	GPIO15_2	0x40e104e4
1404 #define	GPIO16_2	0x40e104e8
1405 #define	GPIO17_2	0x40e104ec
1406 
1407 #define	GPIO74		0x40e104f0
1408 #define	GPIO75		0x40e104f4
1409 #define	GPIO76		0x40e104f8
1410 #define	GPIO77		0x40e104fc
1411 #define	GPIO78		0x40e10500
1412 #define	GPIO79		0x40e10504
1413 #define	GPIO80		0x40e10508
1414 #define	GPIO81		0x40e1050c
1415 #define	GPIO82		0x40e10510
1416 #define	GPIO83		0x40e10514
1417 #define	GPIO84		0x40e10518
1418 #define	GPIO85		0x40e1051c
1419 #define	GPIO86		0x40e10520
1420 #define	GPIO87		0x40e10524
1421 #define	GPIO88		0x40e10528
1422 #define	GPIO89		0x40e1052c
1423 #define	GPIO90		0x40e10530
1424 #define	GPIO91		0x40e10534
1425 #define	GPIO92		0x40e10538
1426 #define	GPIO93		0x40e1053c
1427 #define	GPIO94		0x40e10540
1428 #define	GPIO95		0x40e10544
1429 #define	GPIO96		0x40e10548
1430 #define	GPIO97		0x40e1054c
1431 #define	GPIO98		0x40e10550
1432 
1433 #define	GPIO99		0x40e10600
1434 #define	GPIO100		0x40e10604
1435 #define	GPIO101		0x40e10608
1436 #define	GPIO102		0x40e1060c
1437 #define	GPIO103		0x40e10610
1438 #define	GPIO104		0x40e10614
1439 #define	GPIO105		0x40e10618
1440 #define	GPIO106		0x40e1061c
1441 #define	GPIO107		0x40e10620
1442 #define	GPIO108		0x40e10624
1443 #define	GPIO109		0x40e10628
1444 #define	GPIO110		0x40e1062c
1445 #define	GPIO111		0x40e10630
1446 #define	GPIO112		0x40e10634
1447 
1448 #define	GPIO113		0x40e10638
1449 #define	GPIO114		0x40e1063c
1450 #define	GPIO115		0x40e10640
1451 #define	GPIO116		0x40e10644
1452 #define	GPIO117		0x40e10648
1453 #define	GPIO118		0x40e1064c
1454 #define	GPIO119		0x40e10650
1455 #define	GPIO120		0x40e10654
1456 #define	GPIO121		0x40e10658
1457 #define	GPIO122		0x40e1065c
1458 #define	GPIO123		0x40e10660
1459 #define	GPIO124		0x40e10664
1460 #define	GPIO125		0x40e10668
1461 #define	GPIO126		0x40e1066c
1462 #define	GPIO127		0x40e10670
1463 
1464 #define	GPIO0_2		0x40e10674
1465 #define	GPIO1_2		0x40e10678
1466 #define	GPIO2_2		0x40e1067c
1467 #define	GPIO3_2		0x40e10680
1468 #define	GPIO4_2		0x40e10684
1469 #define	GPIO5_2		0x40e10688
1470 
1471 /* PXA300 and PXA310 */
1472 #elif	defined(CONFIG_CPU_PXA300) || defined(CONFIG_CPU_PXA310)
1473 #define	DF_IO0		0x40e10220
1474 #define	DF_IO1		0x40e10228
1475 #define	DF_IO2		0x40e10230
1476 #define	DF_IO3		0x40e10238
1477 #define	DF_IO4		0x40e10258
1478 #define	DF_IO5		0x40e10260
1479 #define	DF_IO7		0x40e10270
1480 #define	DF_IO6		0x40e10268
1481 #define	DF_IO8		0x40e10224
1482 #define	DF_IO9		0x40e1022c
1483 #define	DF_IO10		0x40e10234
1484 #define	DF_IO11		0x40e1023c
1485 #define	DF_IO12		0x40e1025c
1486 #define	DF_IO13		0x40e10264
1487 #define	DF_IO14		0x40e1026c
1488 #define	DF_IO15		0x40e10274
1489 #define	DF_CLE_NOE	0x40e10240
1490 #define	DF_ALE_nWE	0x40e1020c
1491 #define	DF_SCLK_E	0x40e10250
1492 #define	nCS0		0x40e100c4
1493 #define	nCS1		0x40e100c0
1494 #define	nBE0		0x40e10204
1495 #define	nBE1		0x40e10208
1496 #define	nLUA		0x40e10244
1497 #define	nLLA		0x40e10254
1498 #define	DF_ADDR0	0x40e10210
1499 #define	DF_ADDR1	0x40e10214
1500 #define	DF_ADDR2	0x40e10218
1501 #define	DF_ADDR3	0x40e1021c
1502 #define	DF_INT_RnB	0x40e100c8
1503 #define	DF_nCS0		0x40e10248
1504 #define	DF_nCS1		0x40e10278
1505 #define	DF_nWE		0x40e100cc
1506 #define	DF_nRE		0x40e10200
1507 
1508 #define	GPIO0		0x40e100b4
1509 #define	GPIO1		0x40e100b8
1510 #define	GPIO2		0x40e100bc
1511 #define	GPIO3		0x40e1027c
1512 #define	GPIO4		0x40e10280
1513 
1514 #define	GPIO5		0x40e10284
1515 #define	GPIO6		0x40e10288
1516 #define	GPIO7		0x40e1028c
1517 #define	GPIO8		0x40e10290
1518 #define	GPIO9		0x40e10294
1519 #define	GPIO10		0x40e10298
1520 #define	GPIO11		0x40e1029c
1521 #define	GPIO12		0x40e102a0
1522 #define	GPIO13		0x40e102a4
1523 #define	GPIO14		0x40e102a8
1524 #define	GPIO15		0x40e102ac
1525 #define	GPIO16		0x40e102b0
1526 #define	GPIO17		0x40e102b4
1527 #define	GPIO18		0x40e102b8
1528 #define	GPIO19		0x40e102bc
1529 #define	GPIO20		0x40e102c0
1530 #define	GPIO21		0x40e102c4
1531 #define	GPIO22		0x40e102c8
1532 #define	GPIO23		0x40e102cc
1533 #define	GPIO24		0x40e102d0
1534 #define	GPIO25		0x40e102d4
1535 #define	GPIO26		0x40e102d8
1536 
1537 #define	GPIO27		0x40e10400
1538 #define	GPIO28		0x40e10404
1539 #define	GPIO29		0x40e10408
1540 #define	ULPI_STP	0x40e1040c
1541 #define	ULPI_NXT	0x40e10410
1542 #define	ULPI_DIR	0x40e10414
1543 #define	GPIO30		0x40e10418
1544 #define	GPIO31		0x40e1041c
1545 #define	GPIO32		0x40e10420
1546 #define	GPIO33		0x40e10424
1547 #define	GPIO34		0x40e10428
1548 #define	GPIO35		0x40e1042c
1549 #define	GPIO36		0x40e10430
1550 #define	GPIO37		0x40e10434
1551 #define	GPIO38		0x40e10438
1552 #define	GPIO39		0x40e1043c
1553 #define	GPIO40		0x40e10440
1554 #define	GPIO41		0x40e10444
1555 #define	GPIO42		0x40e10448
1556 #define	GPIO43		0x40e1044c
1557 #define	GPIO44		0x40e10450
1558 #define	GPIO45		0x40e10454
1559 #define	GPIO46		0x40e10458
1560 #define	GPIO47		0x40e1045c
1561 #define	GPIO48		0x40e10460
1562 
1563 #define	GPIO49		0x40e10464
1564 #define	GPIO50		0x40e10468
1565 #define	GPIO51		0x40e1046c
1566 #define	GPIO52		0x40e10470
1567 #define	GPIO53		0x40e10474
1568 #define	GPIO54		0x40e10478
1569 #define	GPIO55		0x40e1047c
1570 #define	GPIO56		0x40e10480
1571 #define	GPIO57		0x40e10484
1572 #define	GPIO58		0x40e10488
1573 #define	GPIO59		0x40e1048c
1574 #define	GPIO60		0x40e10490
1575 #define	GPIO61		0x40e10494
1576 #define	GPIO62		0x40e10498
1577 #define	GPIO63		0x40e1049c
1578 #define	GPIO64		0x40e104a0
1579 #define	GPIO65		0x40e104a4
1580 #define	GPIO66		0x40e104a8
1581 #define	GPIO67		0x40e104ac
1582 #define	GPIO68		0x40e104b0
1583 #define	GPIO69		0x40e104b4
1584 #define	GPIO70		0x40e104b8
1585 #define	GPIO71		0x40e104bc
1586 #define	GPIO72		0x40e104c0
1587 #define	GPIO73		0x40e104c4
1588 #define	GPIO74		0x40e104c8
1589 #define	GPIO75		0x40e104cc
1590 #define	GPIO76		0x40e104d0
1591 #define	GPIO77		0x40e104d4
1592 #define	GPIO78		0x40e104d8
1593 #define	GPIO79		0x40e104dc
1594 #define	GPIO80		0x40e104e0
1595 #define	GPIO81		0x40e104e4
1596 #define	GPIO82		0x40e104e8
1597 #define	GPIO83		0x40e104ec
1598 #define	GPIO84		0x40e104f0
1599 #define	GPIO85		0x40e104f4
1600 #define	GPIO86		0x40e104f8
1601 #define	GPIO87		0x40e104fc
1602 #define	GPIO88		0x40e10500
1603 #define	GPIO89		0x40e10504
1604 #define	GPIO90		0x40e10508
1605 #define	GPIO91		0x40e1050c
1606 #define	GPIO92		0x40e10510
1607 #define	GPIO93		0x40e10514
1608 #define	GPIO94		0x40e10518
1609 #define	GPIO95		0x40e1051c
1610 #define	GPIO96		0x40e10520
1611 #define	GPIO97		0x40e10524
1612 #define	GPIO98		0x40e10528
1613 
1614 #define	GPIO99		0x40e10600
1615 #define	GPIO100		0x40e10604
1616 #define	GPIO101		0x40e10608
1617 #define	GPIO102		0x40e1060c
1618 #define	GPIO103		0x40e10610
1619 #define	GPIO104		0x40e10614
1620 #define	GPIO105		0x40e10618
1621 #define	GPIO106		0x40e1061c
1622 #define	GPIO107		0x40e10620
1623 #define	GPIO108		0x40e10624
1624 #define	GPIO109		0x40e10628
1625 #define	GPIO110		0x40e1062c
1626 #define	GPIO111		0x40e10630
1627 #define	GPIO112		0x40e10634
1628 
1629 #define	GPIO113		0x40e10638
1630 #define	GPIO114		0x40e1063c
1631 #define	GPIO115		0x40e10640
1632 #define	GPIO116		0x40e10644
1633 #define	GPIO117		0x40e10648
1634 #define	GPIO118		0x40e1064c
1635 #define	GPIO119		0x40e10650
1636 #define	GPIO120		0x40e10654
1637 #define	GPIO121		0x40e10658
1638 #define	GPIO122		0x40e1065c
1639 #define	GPIO123		0x40e10660
1640 #define	GPIO124		0x40e10664
1641 #define	GPIO125		0x40e10668
1642 #define	GPIO126		0x40e1066c
1643 #define	GPIO127		0x40e10670
1644 
1645 #define	GPIO0_2		0x40e10674
1646 #define	GPIO1_2		0x40e10678
1647 #define	GPIO2_2		0x40e102dc
1648 #define	GPIO3_2		0x40e102e0
1649 #define	GPIO4_2		0x40e102e4
1650 #define	GPIO5_2		0x40e102e8
1651 #define	GPIO6_2		0x40e102ec
1652 
1653 #ifndef	CONFIG_CPU_PXA300	/* PXA310 only */
1654 #define	GPIO7_2		0x40e1052c
1655 #define	GPIO8_2		0x40e10530
1656 #define	GPIO9_2		0x40e10534
1657 #define	GPIO10_2	0x40e10538
1658 #endif
1659 #endif
1660 
1661 #ifdef CONFIG_CPU_MONAHANS
1662 /* MFPR Bit Definitions, see 4-10, Vol. 1 */
1663 #define PULL_SEL	0x8000
1664 #define PULLUP_EN	0x4000
1665 #define PULLDOWN_EN	0x2000
1666 
1667 #define DRIVE_FAST_1mA	0x0
1668 #define DRIVE_FAST_2mA	0x400
1669 #define DRIVE_FAST_3mA	0x800
1670 #define DRIVE_FAST_4mA	0xC00
1671 #define DRIVE_SLOW_6mA	0x1000
1672 #define DRIVE_FAST_6mA	0x1400
1673 #define DRIVE_SLOW_10mA	0x1800
1674 #define DRIVE_FAST_10mA	0x1C00
1675 
1676 #define SLEEP_SEL	0x200
1677 #define SLEEP_DATA	0x100
1678 #define SLEEP_OE_N	0x80
1679 #define EDGE_CLEAR	0x40
1680 #define EDGE_FALL_EN	0x20
1681 #define EDGE_RISE_EN	0x10
1682 
1683 #define AF_SEL_0	0x0	/* Alternate function 0 (reset state) */
1684 #define AF_SEL_1	0x1	/* Alternate function 1 */
1685 #define AF_SEL_2	0x2	/* Alternate function 2 */
1686 #define AF_SEL_3	0x3	/* Alternate function 3 */
1687 #define AF_SEL_4	0x4	/* Alternate function 4 */
1688 #define AF_SEL_5	0x5	/* Alternate function 5 */
1689 #define AF_SEL_6	0x6	/* Alternate function 6 */
1690 #define AF_SEL_7	0x7	/* Alternate function 7 */
1691 
1692 #endif /* CONFIG_CPU_MONAHANS */
1693 
1694 /* GPIO alternate function assignments */
1695 
1696 #define GPIO1_RST		1	/* reset */
1697 #define GPIO6_MMCCLK		6	/* MMC Clock */
1698 #define GPIO8_48MHz		7	/* 48 MHz clock output */
1699 #define GPIO8_MMCCS0		8	/* MMC Chip Select 0 */
1700 #define GPIO9_MMCCS1		9	/* MMC Chip Select 1 */
1701 #define GPIO10_RTCCLK		10	/* real time clock (1 Hz) */
1702 #define GPIO11_3_6MHz		11	/* 3.6 MHz oscillator out */
1703 #define GPIO12_32KHz		12	/* 32 kHz out */
1704 #define GPIO13_MBGNT		13	/* memory controller grant */
1705 #define GPIO14_MBREQ		14	/* alternate bus master request */
1706 #define GPIO15_nCS_1		15	/* chip select 1 */
1707 #define GPIO16_PWM0		16	/* PWM0 output */
1708 #define GPIO17_PWM1		17	/* PWM1 output */
1709 #define GPIO18_RDY		18	/* Ext. Bus Ready */
1710 #define GPIO19_DREQ1		19	/* External DMA Request */
1711 #define GPIO20_DREQ0		20	/* External DMA Request */
1712 #define GPIO23_SCLK		23	/* SSP clock */
1713 #define GPIO24_SFRM		24	/* SSP Frame */
1714 #define GPIO25_STXD		25	/* SSP transmit */
1715 #define GPIO26_SRXD		26	/* SSP receive */
1716 #define GPIO27_SEXTCLK		27	/* SSP ext_clk */
1717 #define GPIO28_BITCLK		28	/* AC97/I2S bit_clk */
1718 #define GPIO29_SDATA_IN		29	/* AC97 Sdata_in0 / I2S Sdata_in */
1719 #define GPIO30_SDATA_OUT	30	/* AC97/I2S Sdata_out */
1720 #define GPIO31_SYNC		31	/* AC97/I2S sync */
1721 #define GPIO32_SDATA_IN1	32	/* AC97 Sdata_in1 */
1722 #define GPIO33_nCS_5		33	/* chip select 5 */
1723 #define GPIO34_FFRXD		34	/* FFUART receive */
1724 #define GPIO34_MMCCS0		34	/* MMC Chip Select 0 */
1725 #define GPIO35_FFCTS		35	/* FFUART Clear to send */
1726 #define GPIO36_FFDCD		36	/* FFUART Data carrier detect */
1727 #define GPIO37_FFDSR		37	/* FFUART data set ready */
1728 #define GPIO38_FFRI		38	/* FFUART Ring Indicator */
1729 #define GPIO39_MMCCS1		39	/* MMC Chip Select 1 */
1730 #define GPIO39_FFTXD		39	/* FFUART transmit data */
1731 #define GPIO40_FFDTR		40	/* FFUART data terminal Ready */
1732 #define GPIO41_FFRTS		41	/* FFUART request to send */
1733 #define GPIO42_BTRXD		42	/* BTUART receive data */
1734 #define GPIO43_BTTXD		43	/* BTUART transmit data */
1735 #define GPIO44_BTCTS		44	/* BTUART clear to send */
1736 #define GPIO45_BTRTS		45	/* BTUART request to send */
1737 #define GPIO46_ICPRXD		46	/* ICP receive data */
1738 #define GPIO46_STRXD		46	/* STD_UART receive data */
1739 #define GPIO47_ICPTXD		47	/* ICP transmit data */
1740 #define GPIO47_STTXD		47	/* STD_UART transmit data */
1741 #define GPIO48_nPOE		48	/* Output Enable for Card Space */
1742 #define GPIO49_nPWE		49	/* Write Enable for Card Space */
1743 #define GPIO50_nPIOR		50	/* I/O Read for Card Space */
1744 #define GPIO51_nPIOW		51	/* I/O Write for Card Space */
1745 #define GPIO52_nPCE_1		52	/* Card Enable for Card Space */
1746 #define GPIO53_nPCE_2		53	/* Card Enable for Card Space */
1747 #define GPIO53_MMCCLK		53	/* MMC Clock */
1748 #define GPIO54_MMCCLK		54	/* MMC Clock */
1749 #define GPIO54_pSKTSEL		54	/* Socket Select for Card Space */
1750 #define GPIO55_nPREG		55	/* Card Address bit 26 */
1751 #define GPIO56_nPWAIT		56	/* Wait signal for Card Space */
1752 #define GPIO57_nIOIS16		57	/* Bus Width select for I/O Card Space */
1753 #define GPIO58_LDD_0		58	/* LCD data pin 0 */
1754 #define GPIO59_LDD_1		59	/* LCD data pin 1 */
1755 #define GPIO60_LDD_2		60	/* LCD data pin 2 */
1756 #define GPIO61_LDD_3		61	/* LCD data pin 3 */
1757 #define GPIO62_LDD_4		62	/* LCD data pin 4 */
1758 #define GPIO63_LDD_5		63	/* LCD data pin 5 */
1759 #define GPIO64_LDD_6		64	/* LCD data pin 6 */
1760 #define GPIO65_LDD_7		65	/* LCD data pin 7 */
1761 #define GPIO66_LDD_8		66	/* LCD data pin 8 */
1762 #define GPIO66_MBREQ		66	/* alternate bus master req */
1763 #define GPIO67_LDD_9		67	/* LCD data pin 9 */
1764 #define GPIO67_MMCCS0		67	/* MMC Chip Select 0 */
1765 #define GPIO68_LDD_10		68	/* LCD data pin 10 */
1766 #define GPIO68_MMCCS1		68	/* MMC Chip Select 1 */
1767 #define GPIO69_LDD_11		69	/* LCD data pin 11 */
1768 #define GPIO69_MMCCLK		69	/* MMC_CLK */
1769 #define GPIO70_LDD_12		70	/* LCD data pin 12 */
1770 #define GPIO70_RTCCLK		70	/* Real Time clock (1 Hz) */
1771 #define GPIO71_LDD_13		71	/* LCD data pin 13 */
1772 #define GPIO71_3_6MHz		71	/* 3.6 MHz Oscillator clock */
1773 #define GPIO72_LDD_14		72	/* LCD data pin 14 */
1774 #define GPIO72_32kHz		72	/* 32 kHz clock */
1775 #define GPIO73_LDD_15		73	/* LCD data pin 15 */
1776 #define GPIO73_MBGNT		73	/* Memory controller grant */
1777 #define GPIO74_LCD_FCLK		74	/* LCD Frame clock */
1778 #define GPIO75_LCD_LCLK		75	/* LCD line clock */
1779 #define GPIO76_LCD_PCLK		76	/* LCD Pixel clock */
1780 #define GPIO77_LCD_ACBIAS	77	/* LCD AC Bias */
1781 #define GPIO78_nCS_2		78	/* chip select 2 */
1782 #define GPIO79_nCS_3		79	/* chip select 3 */
1783 #define GPIO80_nCS_4		80	/* chip select 4 */
1784 
1785 /* GPIO alternate function mode & direction */
1786 
1787 #define GPIO_IN			0x000
1788 #define GPIO_OUT		0x080
1789 #define GPIO_ALT_FN_1_IN	0x100
1790 #define GPIO_ALT_FN_1_OUT	0x180
1791 #define GPIO_ALT_FN_2_IN	0x200
1792 #define GPIO_ALT_FN_2_OUT	0x280
1793 #define GPIO_ALT_FN_3_IN	0x300
1794 #define GPIO_ALT_FN_3_OUT	0x380
1795 #define GPIO_MD_MASK_NR		0x07f
1796 #define GPIO_MD_MASK_DIR	0x080
1797 #define GPIO_MD_MASK_FN		0x300
1798 
1799 #define GPIO1_RTS_MD		( 1 | GPIO_ALT_FN_1_IN)
1800 #define GPIO6_MMCCLK_MD		( 6 | GPIO_ALT_FN_1_OUT)
1801 #define GPIO8_48MHz_MD		( 8 | GPIO_ALT_FN_1_OUT)
1802 #define GPIO8_MMCCS0_MD		( 8 | GPIO_ALT_FN_1_OUT)
1803 #define GPIO9_MMCCS1_MD		( 9 | GPIO_ALT_FN_1_OUT)
1804 #define GPIO10_RTCCLK_MD	(10 | GPIO_ALT_FN_1_OUT)
1805 #define GPIO11_3_6MHz_MD	(11 | GPIO_ALT_FN_1_OUT)
1806 #define GPIO12_32KHz_MD		(12 | GPIO_ALT_FN_1_OUT)
1807 #define GPIO13_MBGNT_MD		(13 | GPIO_ALT_FN_2_OUT)
1808 #define GPIO14_MBREQ_MD		(14 | GPIO_ALT_FN_1_IN)
1809 #define GPIO15_nCS_1_MD		(15 | GPIO_ALT_FN_2_OUT)
1810 #define GPIO16_PWM0_MD		(16 | GPIO_ALT_FN_2_OUT)
1811 #define GPIO17_PWM1_MD		(17 | GPIO_ALT_FN_2_OUT)
1812 #define GPIO18_RDY_MD		(18 | GPIO_ALT_FN_1_IN)
1813 #define GPIO19_DREQ1_MD		(19 | GPIO_ALT_FN_1_IN)
1814 #define GPIO20_DREQ0_MD		(20 | GPIO_ALT_FN_1_IN)
1815 #define GPIO23_SCLK_md		(23 | GPIO_ALT_FN_2_OUT)
1816 #define GPIO24_SFRM_MD		(24 | GPIO_ALT_FN_2_OUT)
1817 #define GPIO25_STXD_MD		(25 | GPIO_ALT_FN_2_OUT)
1818 #define GPIO26_SRXD_MD		(26 | GPIO_ALT_FN_1_IN)
1819 #define GPIO27_SEXTCLK_MD	(27 | GPIO_ALT_FN_1_IN)
1820 #define GPIO28_BITCLK_AC97_MD	(28 | GPIO_ALT_FN_1_IN)
1821 #define GPIO28_BITCLK_I2S_MD	(28 | GPIO_ALT_FN_2_IN)
1822 #define GPIO29_SDATA_IN_AC97_MD (29 | GPIO_ALT_FN_1_IN)
1823 #define GPIO29_SDATA_IN_I2S_MD	(29 | GPIO_ALT_FN_2_IN)
1824 #define GPIO30_SDATA_OUT_AC97_MD	(30 | GPIO_ALT_FN_2_OUT)
1825 #define GPIO30_SDATA_OUT_I2S_MD (30 | GPIO_ALT_FN_1_OUT)
1826 #define GPIO31_SYNC_AC97_MD	(31 | GPIO_ALT_FN_2_OUT)
1827 #define GPIO31_SYNC_I2S_MD	(31 | GPIO_ALT_FN_1_OUT)
1828 #define GPIO32_SDATA_IN1_AC97_MD	(32 | GPIO_ALT_FN_1_IN)
1829 #define GPIO33_nCS_5_MD		(33 | GPIO_ALT_FN_2_OUT)
1830 #define GPIO34_FFRXD_MD		(34 | GPIO_ALT_FN_1_IN)
1831 #define GPIO34_MMCCS0_MD	(34 | GPIO_ALT_FN_2_OUT)
1832 #define GPIO35_FFCTS_MD		(35 | GPIO_ALT_FN_1_IN)
1833 #define GPIO36_FFDCD_MD		(36 | GPIO_ALT_FN_1_IN)
1834 #define GPIO37_FFDSR_MD		(37 | GPIO_ALT_FN_1_IN)
1835 #define GPIO38_FFRI_MD		(38 | GPIO_ALT_FN_1_IN)
1836 #define GPIO39_MMCCS1_MD	(39 | GPIO_ALT_FN_1_OUT)
1837 #define GPIO39_FFTXD_MD		(39 | GPIO_ALT_FN_2_OUT)
1838 #define GPIO40_FFDTR_MD		(40 | GPIO_ALT_FN_2_OUT)
1839 #define GPIO41_FFRTS_MD		(41 | GPIO_ALT_FN_2_OUT)
1840 #define GPIO42_BTRXD_MD		(42 | GPIO_ALT_FN_1_IN)
1841 #define GPIO43_BTTXD_MD		(43 | GPIO_ALT_FN_2_OUT)
1842 #define GPIO44_BTCTS_MD		(44 | GPIO_ALT_FN_1_IN)
1843 #define GPIO45_BTRTS_MD		(45 | GPIO_ALT_FN_2_OUT)
1844 #define GPIO46_ICPRXD_MD	(46 | GPIO_ALT_FN_1_IN)
1845 #define GPIO46_STRXD_MD		(46 | GPIO_ALT_FN_2_IN)
1846 #define GPIO47_ICPTXD_MD	(47 | GPIO_ALT_FN_2_OUT)
1847 #define GPIO47_STTXD_MD		(47 | GPIO_ALT_FN_1_OUT)
1848 #define GPIO48_nPOE_MD		(48 | GPIO_ALT_FN_2_OUT)
1849 #define GPIO49_nPWE_MD		(49 | GPIO_ALT_FN_2_OUT)
1850 #define GPIO50_nPIOR_MD		(50 | GPIO_ALT_FN_2_OUT)
1851 #define GPIO51_nPIOW_MD		(51 | GPIO_ALT_FN_2_OUT)
1852 #define GPIO52_nPCE_1_MD	(52 | GPIO_ALT_FN_2_OUT)
1853 #define GPIO53_nPCE_2_MD	(53 | GPIO_ALT_FN_2_OUT)
1854 #define GPIO53_MMCCLK_MD	(53 | GPIO_ALT_FN_1_OUT)
1855 #define GPIO54_MMCCLK_MD	(54 | GPIO_ALT_FN_1_OUT)
1856 #define GPIO54_pSKTSEL_MD	(54 | GPIO_ALT_FN_2_OUT)
1857 #define GPIO55_nPREG_MD		(55 | GPIO_ALT_FN_2_OUT)
1858 #define GPIO56_nPWAIT_MD	(56 | GPIO_ALT_FN_1_IN)
1859 #define GPIO57_nIOIS16_MD	(57 | GPIO_ALT_FN_1_IN)
1860 #define GPIO58_LDD_0_MD		(58 | GPIO_ALT_FN_2_OUT)
1861 #define GPIO59_LDD_1_MD		(59 | GPIO_ALT_FN_2_OUT)
1862 #define GPIO60_LDD_2_MD		(60 | GPIO_ALT_FN_2_OUT)
1863 #define GPIO61_LDD_3_MD		(61 | GPIO_ALT_FN_2_OUT)
1864 #define GPIO62_LDD_4_MD		(62 | GPIO_ALT_FN_2_OUT)
1865 #define GPIO63_LDD_5_MD		(63 | GPIO_ALT_FN_2_OUT)
1866 #define GPIO64_LDD_6_MD		(64 | GPIO_ALT_FN_2_OUT)
1867 #define GPIO65_LDD_7_MD		(65 | GPIO_ALT_FN_2_OUT)
1868 #define GPIO66_LDD_8_MD		(66 | GPIO_ALT_FN_2_OUT)
1869 #define GPIO66_MBREQ_MD		(66 | GPIO_ALT_FN_1_IN)
1870 #define GPIO67_LDD_9_MD		(67 | GPIO_ALT_FN_2_OUT)
1871 #define GPIO67_MMCCS0_MD	(67 | GPIO_ALT_FN_1_OUT)
1872 #define GPIO68_LDD_10_MD	(68 | GPIO_ALT_FN_2_OUT)
1873 #define GPIO68_MMCCS1_MD	(68 | GPIO_ALT_FN_1_OUT)
1874 #define GPIO69_LDD_11_MD	(69 | GPIO_ALT_FN_2_OUT)
1875 #define GPIO69_MMCCLK_MD	(69 | GPIO_ALT_FN_1_OUT)
1876 #define GPIO70_LDD_12_MD	(70 | GPIO_ALT_FN_2_OUT)
1877 #define GPIO70_RTCCLK_MD	(70 | GPIO_ALT_FN_1_OUT)
1878 #define GPIO71_LDD_13_MD	(71 | GPIO_ALT_FN_2_OUT)
1879 #define GPIO71_3_6MHz_MD	(71 | GPIO_ALT_FN_1_OUT)
1880 #define GPIO72_LDD_14_MD	(72 | GPIO_ALT_FN_2_OUT)
1881 #define GPIO72_32kHz_MD		(72 | GPIO_ALT_FN_1_OUT)
1882 #define GPIO73_LDD_15_MD	(73 | GPIO_ALT_FN_2_OUT)
1883 #define GPIO73_MBGNT_MD		(73 | GPIO_ALT_FN_1_OUT)
1884 #define GPIO74_LCD_FCLK_MD	(74 | GPIO_ALT_FN_2_OUT)
1885 #define GPIO75_LCD_LCLK_MD	(75 | GPIO_ALT_FN_2_OUT)
1886 #define GPIO76_LCD_PCLK_MD	(76 | GPIO_ALT_FN_2_OUT)
1887 #define GPIO77_LCD_ACBIAS_MD	(77 | GPIO_ALT_FN_2_OUT)
1888 #define GPIO78_nCS_2_MD		(78 | GPIO_ALT_FN_2_OUT)
1889 #define GPIO79_nCS_3_MD		(79 | GPIO_ALT_FN_2_OUT)
1890 #define GPIO80_nCS_4_MD		(80 | GPIO_ALT_FN_2_OUT)
1891 
1892 #define GPIO117_SCL		(117 | GPIO_ALT_FN_1_OUT)
1893 #define GPIO118_SDA		(118 | GPIO_ALT_FN_1_OUT)
1894 
1895 /*
1896  * Power Manager
1897  */
1898 #ifdef CONFIG_CPU_MONAHANS
1899 
1900 #define ASCR		0x40F40000  /* Application Subsystem Power Status/Control Register */
1901 #define ARSR		0x40F40004  /* Application Subsystem Reset Status Register */
1902 #define AD3ER		0x40F40008  /* Application Subsystem D3 state Wakeup Enable Register */
1903 #define AD3SR		0x40F4000C  /* Application Subsystem D3 state Wakeup Status Register */
1904 #define AD2D0ER		0x40F40010  /* Application Subsystem D2 to D0 state Wakeup Enable Register */
1905 #define AD2D0SR		0x40F40014  /* Application Subsystem D2 to D0 state Wakeup Status Register */
1906 #define AD2D1ER		0x40F40018  /* Application Subsystem D2 to D1 state Wakeup Enable Register */
1907 #define AD2D1SR		0x40F4001C  /* Application Subsystem D2 to D1 state Wakeup Status Register */
1908 #define AD1D0ER		0x40F40020  /* Application Subsystem D1 to D0 state Wakeup Enable Register */
1909 #define AD1D0SR		0x40F40024  /* Application Subsystem D1 to D0 state Wakeup Status Register */
1910 #define ASDCNT		0x40F40028  /* Application Subsystem SRAM Drowsy Count Register */
1911 #define AD3R		0x40F40030  /* Application Subsystem D3 State Configuration Register */
1912 #define AD2R		0x40F40034  /* Application Subsystem D2 State Configuration Register */
1913 #define AD1R		0x40F40038  /* Application Subsystem D1 State Configuration Register */
1914 
1915 #define PMCR		0x40F50000  /* Power Manager Control Register */
1916 #define PSR		0x40F50004  /* Power Manager S2 Status Register */
1917 #define PSPR		0x40F50008  /* Power Manager Scratch Pad Register */
1918 #define PCFR		0x40F5000C  /* Power Manager General Configuration Register */
1919 #define PWER		0x40F50010  /* Power Manager Wake-up Enable Register */
1920 #define PWSR		0x40F50014  /* Power Manager Wake-up Status Register */
1921 #define PECR		0x40F50018  /* Power Manager EXT_WAKEUP[1:0] Control Register */
1922 #define DCDCSR		0x40F50080  /* DC-DC Controller Status Register */
1923 #define PVCR		0x40F50100  /* Power Manager Voltage Change Control Register */
1924 #define    PCMD(x) (0x40F50110 + x*4)
1925 #define    PCMD0   (0x40F50110 + 0 * 4)
1926 #define    PCMD1   (0x40F50110 + 1 * 4)
1927 #define    PCMD2   (0x40F50110 + 2 * 4)
1928 #define    PCMD3   (0x40F50110 + 3 * 4)
1929 #define    PCMD4   (0x40F50110 + 4 * 4)
1930 #define    PCMD5   (0x40F50110 + 5 * 4)
1931 #define    PCMD6   (0x40F50110 + 6 * 4)
1932 #define    PCMD7   (0x40F50110 + 7 * 4)
1933 #define    PCMD8   (0x40F50110 + 8 * 4)
1934 #define    PCMD9   (0x40F50110 + 9 * 4)
1935 #define    PCMD10  (0x40F50110 + 10 * 4)
1936 #define    PCMD11  (0x40F50110 + 11 * 4)
1937 #define    PCMD12  (0x40F50110 + 12 * 4)
1938 #define    PCMD13  (0x40F50110 + 13 * 4)
1939 #define    PCMD14  (0x40F50110 + 14 * 4)
1940 #define    PCMD15  (0x40F50110 + 15 * 4)
1941 #define    PCMD16  (0x40F50110 + 16 * 4)
1942 #define    PCMD17  (0x40F50110 + 17 * 4)
1943 #define    PCMD18  (0x40F50110 + 18 * 4)
1944 #define    PCMD19  (0x40F50110 + 19 * 4)
1945 #define    PCMD20  (0x40F50110 + 20 * 4)
1946 #define    PCMD21  (0x40F50110 + 21 * 4)
1947 #define    PCMD22  (0x40F50110 + 22 * 4)
1948 #define    PCMD23  (0x40F50110 + 23 * 4)
1949 #define    PCMD24  (0x40F50110 + 24 * 4)
1950 #define    PCMD25  (0x40F50110 + 25 * 4)
1951 #define    PCMD26  (0x40F50110 + 26 * 4)
1952 #define    PCMD27  (0x40F50110 + 27 * 4)
1953 #define    PCMD28  (0x40F50110 + 28 * 4)
1954 #define    PCMD29  (0x40F50110 + 29 * 4)
1955 #define    PCMD30  (0x40F50110 + 30 * 4)
1956 #define    PCMD31  (0x40F50110 + 31 * 4)
1957 
1958 #define    PCMD_MBC    (1<<12)
1959 #define    PCMD_DCE    (1<<11)
1960 #define    PCMD_LC     (1<<10)
1961 #define    PCMD_SQC    (3<<8)  /* only 00 and 01 are valid */
1962 
1963 #define PVCR_FVC                   (0x1 << 28)
1964 #define PVCR_VCSA                  (0x1<<14)
1965 #define PVCR_CommandDelay          (0xf80)
1966 #define PVCR_ReadPointer           0x01f00000
1967 #define PVCR_SlaveAddress          (0x7f)
1968 
1969 #else /* ifdef CONFIG_CPU_MONAHANS */
1970 
1971 #define PMCR		0x40F00000  /* Power Manager Control Register */
1972 #define PSSR		0x40F00004  /* Power Manager Sleep Status Register */
1973 #define PSPR		0x40F00008  /* Power Manager Scratch Pad Register */
1974 #define PWER		0x40F0000C  /* Power Manager Wake-up Enable Register */
1975 #define PRER		0x40F00010  /* Power Manager GPIO Rising-Edge Detect Enable Register */
1976 #define PFER		0x40F00014  /* Power Manager GPIO Falling-Edge Detect Enable Register */
1977 #define PEDR		0x40F00018  /* Power Manager GPIO Edge Detect Status Register */
1978 #define PCFR		0x40F0001C  /* Power Manager General Configuration Register */
1979 #define PGSR0		0x40F00020  /* Power Manager GPIO Sleep State Register for GP[31-0] */
1980 #define PGSR1		0x40F00024  /* Power Manager GPIO Sleep State Register for GP[63-32] */
1981 #define PGSR2		0x40F00028  /* Power Manager GPIO Sleep State Register for GP[84-64] */
1982 #define PGSR3		0x40F0002C  /* Power Manager GPIO Sleep State Register for GP[118-96] */
1983 #define RCSR		0x40F00030  /* Reset Controller Status Register */
1984 
1985 #define	   PSLR	   0x40F00034	/* Power Manager Sleep Config Register */
1986 #define	   PSTR	   0x40F00038	/* Power Manager Standby Config Register */
1987 #define	   PSNR	   0x40F0003C	/* Power Manager Sense Config Register */
1988 #define	   PVCR	   0x40F00040	/* Power Manager VoltageControl Register */
1989 #define	   PKWR	   0x40F00050	/* Power Manager KB Wake-up Enable Reg */
1990 #define	   PKSR	   0x40F00054	/* Power Manager KB Level-Detect Register */
1991 #define	   PCMD(x) (0x40F00080 + x*4)
1992 #define	   PCMD0   (0x40F00080 + 0 * 4)
1993 #define	   PCMD1   (0x40F00080 + 1 * 4)
1994 #define	   PCMD2   (0x40F00080 + 2 * 4)
1995 #define	   PCMD3   (0x40F00080 + 3 * 4)
1996 #define	   PCMD4   (0x40F00080 + 4 * 4)
1997 #define	   PCMD5   (0x40F00080 + 5 * 4)
1998 #define	   PCMD6   (0x40F00080 + 6 * 4)
1999 #define	   PCMD7   (0x40F00080 + 7 * 4)
2000 #define	   PCMD8   (0x40F00080 + 8 * 4)
2001 #define	   PCMD9   (0x40F00080 + 9 * 4)
2002 #define	   PCMD10  (0x40F00080 + 10 * 4)
2003 #define	   PCMD11  (0x40F00080 + 11 * 4)
2004 #define	   PCMD12  (0x40F00080 + 12 * 4)
2005 #define	   PCMD13  (0x40F00080 + 13 * 4)
2006 #define	   PCMD14  (0x40F00080 + 14 * 4)
2007 #define	   PCMD15  (0x40F00080 + 15 * 4)
2008 #define	   PCMD16  (0x40F00080 + 16 * 4)
2009 #define	   PCMD17  (0x40F00080 + 17 * 4)
2010 #define	   PCMD18  (0x40F00080 + 18 * 4)
2011 #define	   PCMD19  (0x40F00080 + 19 * 4)
2012 #define	   PCMD20  (0x40F00080 + 20 * 4)
2013 #define	   PCMD21  (0x40F00080 + 21 * 4)
2014 #define	   PCMD22  (0x40F00080 + 22 * 4)
2015 #define	   PCMD23  (0x40F00080 + 23 * 4)
2016 #define	   PCMD24  (0x40F00080 + 24 * 4)
2017 #define	   PCMD25  (0x40F00080 + 25 * 4)
2018 #define	   PCMD26  (0x40F00080 + 26 * 4)
2019 #define	   PCMD27  (0x40F00080 + 27 * 4)
2020 #define	   PCMD28  (0x40F00080 + 28 * 4)
2021 #define	   PCMD29  (0x40F00080 + 29 * 4)
2022 #define	   PCMD30  (0x40F00080 + 30 * 4)
2023 #define	   PCMD31  (0x40F00080 + 31 * 4)
2024 
2025 #define	   PCMD_MBC    (1<<12)
2026 #define	   PCMD_DCE    (1<<11)
2027 #define	   PCMD_LC     (1<<10)
2028 /* FIXME:  PCMD_SQC need be checked.   */
2029 #define	   PCMD_SQC    (3<<8)  /* currently only bit 8 is changerable, */
2030 				/* bit 9 should be 0 all day. */
2031 #define PVCR_VCSA		   (0x1<<14)
2032 #define PVCR_CommandDelay	   (0xf80)
2033 /* define MACRO for Power Manager General Configuration Register (PCFR) */
2034 #define PCFR_FVC		   (0x1 << 10)
2035 #define PCFR_PI2C_EN		   (0x1 << 6)
2036 
2037 #define PSSR_OTGPH	(1 << 6)	/* OTG Peripheral control Hold */
2038 #define PSSR_RDH	(1 << 5)	/* Read Disable Hold */
2039 #define PSSR_PH		(1 << 4)	/* Peripheral Control Hold */
2040 #define PSSR_VFS	(1 << 2)	/* VDD Fault Status */
2041 #define PSSR_BFS	(1 << 1)	/* Battery Fault Status */
2042 #define PSSR_SSS	(1 << 0)	/* Software Sleep Status */
2043 
2044 #define PCFR_DS		(1 << 3)	/* Deep Sleep Mode */
2045 #define PCFR_FS		(1 << 2)	/* Float Static Chip Selects */
2046 #define PCFR_FP		(1 << 1)	/* Float PCMCIA controls */
2047 #define PCFR_OPDE	(1 << 0)	/* 3.6864 MHz oscillator power-down enable */
2048 
2049 #define RCSR_GPR	(1 << 3)	/* GPIO Reset */
2050 #define RCSR_SMR	(1 << 2)	/* Sleep Mode */
2051 #define RCSR_WDR	(1 << 1)	/* Watchdog Reset */
2052 #define RCSR_HWR	(1 << 0)	/* Hardware Reset */
2053 
2054 #endif /* CONFIG_CPU_MONAHANS */
2055 
2056 /*
2057  * SSP Serial Port Registers
2058  */
2059 #define SSCR0		0x41000000  /* SSP Control Register 0 */
2060 #define SSCR1		0x41000004  /* SSP Control Register 1 */
2061 #define SSSR		0x41000008  /* SSP Status Register */
2062 #define SSITR		0x4100000C  /* SSP Interrupt Test Register */
2063 #define SSDR		0x41000010  /* (Write / Read) SSP Data Write Register/SSP Data Read Register */
2064 
2065 /*
2066  * MultiMediaCard (MMC) controller
2067  */
2068 #define MMC_STRPCL	0x41100000  /* Control to start and stop MMC clock */
2069 #define MMC_STAT	0x41100004  /* MMC Status Register (read only) */
2070 #define MMC_CLKRT	0x41100008  /* MMC clock rate */
2071 #define MMC_SPI		0x4110000c  /* SPI mode control bits */
2072 #define MMC_CMDAT	0x41100010  /* Command/response/data sequence control */
2073 #define MMC_RESTO	0x41100014  /* Expected response time out */
2074 #define MMC_RDTO	0x41100018  /* Expected data read time out */
2075 #define MMC_BLKLEN	0x4110001c  /* Block length of data transaction */
2076 #define MMC_NOB		0x41100020  /* Number of blocks, for block mode */
2077 #define MMC_PRTBUF	0x41100024  /* Partial MMC_TXFIFO FIFO written */
2078 #define MMC_I_MASK	0x41100028  /* Interrupt Mask */
2079 #define MMC_I_REG	0x4110002c  /* Interrupt Register (read only) */
2080 #define MMC_CMD		0x41100030  /* Index of current command */
2081 #define MMC_ARGH	0x41100034  /* MSW part of the current command argument */
2082 #define MMC_ARGL	0x41100038  /* LSW part of the current command argument */
2083 #define MMC_RES		0x4110003c  /* Response FIFO (read only) */
2084 #define MMC_RXFIFO	0x41100040  /* Receive FIFO (read only) */
2085 #define MMC_TXFIFO	0x41100044  /* Transmit FIFO (write only) */
2086 
2087 
2088 /*
2089  * LCD
2090  */
2091 #define LCCR0		0x44000000  /* LCD Controller Control Register 0 */
2092 #define LCCR1		0x44000004  /* LCD Controller Control Register 1 */
2093 #define LCCR2		0x44000008  /* LCD Controller Control Register 2 */
2094 #define LCCR3		0x4400000C  /* LCD Controller Control Register 3 */
2095 #define DFBR0		0x44000020  /* DMA Channel 0 Frame Branch Register */
2096 #define DFBR1		0x44000024  /* DMA Channel 1 Frame Branch Register */
2097 #define LCSR0		0x44000038  /* LCD Controller Status Register */
2098 #define LCSR1		0x44000034  /* LCD Controller Status Register */
2099 #define LIIDR		0x4400003C  /* LCD Controller Interrupt ID Register */
2100 #define TMEDRGBR	0x44000040  /* TMED RGB Seed Register */
2101 #define TMEDCR		0x44000044  /* TMED Control Register */
2102 
2103 #define FDADR0		0x44000200  /* DMA Channel 0 Frame Descriptor Address Register */
2104 #define FSADR0		0x44000204  /* DMA Channel 0 Frame Source Address Register */
2105 #define FIDR0		0x44000208  /* DMA Channel 0 Frame ID Register */
2106 #define LDCMD0		0x4400020C  /* DMA Channel 0 Command Register */
2107 #define FDADR1		0x44000210  /* DMA Channel 1 Frame Descriptor Address Register */
2108 #define FSADR1		0x44000214  /* DMA Channel 1 Frame Source Address Register */
2109 #define FIDR1		0x44000218  /* DMA Channel 1 Frame ID Register */
2110 #define LDCMD1		0x4400021C  /* DMA Channel 1 Command Register */
2111 
2112 #define LCCR0_ENB	(1 << 0)	/* LCD Controller enable */
2113 #define LCCR0_CMS	(1 << 1)	/* Color = 0, Monochrome = 1 */
2114 #define LCCR0_SDS	(1 << 2)	/* Single Panel = 0, Dual Panel = 1 */
2115 #define LCCR0_LDM	(1 << 3)	/* LCD Disable Done Mask */
2116 #define LCCR0_SFM	(1 << 4)	/* Start of frame mask */
2117 #define LCCR0_IUM	(1 << 5)	/* Input FIFO underrun mask */
2118 #define LCCR0_EFM	(1 << 6)	/* End of Frame mask */
2119 #define LCCR0_PAS	(1 << 7)	/* Passive = 0, Active = 1 */
2120 #define LCCR0_BLE	(1 << 8)	/* Little Endian = 0, Big Endian = 1 */
2121 #define LCCR0_DPD	(1 << 9)	/* Double Pixel mode, 4 pixel value = 0, 8 pixle values = 1 */
2122 #define LCCR0_DIS	(1 << 10)	/* LCD Disable */
2123 #define LCCR0_QDM	(1 << 11)	/* LCD Quick Disable mask */
2124 #define LCCR0_PDD	(0xff << 12)	/* Palette DMA request delay */
2125 #define LCCR0_PDD_S	12
2126 #define LCCR0_BM	(1 << 20)	/* Branch mask */
2127 #define LCCR0_OUM	(1 << 21)	/* Output FIFO underrun mask */
2128 #if defined(CONFIG_CPU_PXA27X)
2129 #define LCCR0_LCDT	(1 << 22)	/* LCD Panel Type */
2130 #define LCCR0_RDSTM	(1 << 23)	/* Read Status Interrupt Mask */
2131 #define LCCR0_CMDIM	(1 << 24)	/* Command Interrupt Mask */
2132 #endif
2133 
2134 #define LCCR1_PPL	Fld (10, 0)	 /* Pixels Per Line - 1 */
2135 #define LCCR1_DisWdth(Pixel)		/* Display Width [1..800 pix.]	*/ \
2136 			(((Pixel) - 1) << FShft (LCCR1_PPL))
2137 
2138 #define LCCR1_HSW	Fld (6, 10)	/* Horizontal Synchronization	  */
2139 #define LCCR1_HorSnchWdth(Tpix)		/* Horizontal Synchronization	  */ \
2140 					/* pulse Width [1..64 Tpix]	  */ \
2141 			(((Tpix) - 1) << FShft (LCCR1_HSW))
2142 
2143 #define LCCR1_ELW	Fld (8, 16)	/* End-of-Line pixel clock Wait	   */
2144 					/* count - 1 [Tpix]		   */
2145 #define LCCR1_EndLnDel(Tpix)		/*  End-of-Line Delay		   */ \
2146 					/*  [1..256 Tpix]		   */ \
2147 			(((Tpix) - 1) << FShft (LCCR1_ELW))
2148 
2149 #define LCCR1_BLW	Fld (8, 24)	/* Beginning-of-Line pixel clock   */
2150 					/* Wait count - 1 [Tpix]	   */
2151 #define LCCR1_BegLnDel(Tpix)		/*  Beginning-of-Line Delay	   */ \
2152 					/*  [1..256 Tpix]		   */ \
2153 			(((Tpix) - 1) << FShft (LCCR1_BLW))
2154 
2155 
2156 #define LCCR2_LPP	Fld (10, 0)	/* Line Per Panel - 1		   */
2157 #define LCCR2_DisHght(Line)		/*  Display Height [1..1024 lines] */ \
2158 			(((Line) - 1) << FShft (LCCR2_LPP))
2159 
2160 #define LCCR2_VSW	Fld (6, 10)	/* Vertical Synchronization pulse  */
2161 					/* Width - 1 [Tln] (L_FCLK)	   */
2162 #define LCCR2_VrtSnchWdth(Tln)		/*  Vertical Synchronization pulse */ \
2163 					/*  Width [1..64 Tln]		   */ \
2164 			(((Tln) - 1) << FShft (LCCR2_VSW))
2165 
2166 #define LCCR2_EFW	Fld (8, 16)	/* End-of-Frame line clock Wait	   */
2167 					/* count [Tln]			   */
2168 #define LCCR2_EndFrmDel(Tln)		/*  End-of-Frame Delay		   */ \
2169 					/*  [0..255 Tln]		   */ \
2170 			((Tln) << FShft (LCCR2_EFW))
2171 
2172 #define LCCR2_BFW	Fld (8, 24)	/* Beginning-of-Frame line clock   */
2173 					/* Wait count [Tln]		   */
2174 #define LCCR2_BegFrmDel(Tln)		/*  Beginning-of-Frame Delay	   */ \
2175 					/*  [0..255 Tln]		   */ \
2176 			((Tln) << FShft (LCCR2_BFW))
2177 
2178 #define LCCR3_API	(0xf << 16)	/* AC Bias pin trasitions per interrupt */
2179 #define LCCR3_API_S	16
2180 #define LCCR3_VSP	(1 << 20)	/* vertical sync polarity */
2181 #define LCCR3_HSP	(1 << 21)	/* horizontal sync polarity */
2182 #define LCCR3_PCP	(1 << 22)	/* pixel clock polarity */
2183 #define LCCR3_OEP	(1 << 23)	/* output enable polarity */
2184 #define LCCR3_DPC	(1 << 27)	/* double pixel clock mode */
2185 
2186 #define LCCR3_PDFOR_0	 (0 << 30)
2187 #define LCCR3_PDFOR_1	 (1 << 30)
2188 #define LCCR3_PDFOR_2	 (2 << 30)
2189 #define LCCR3_PDFOR_3	 (3 << 30)
2190 
2191 
2192 #define LCCR3_PCD	Fld (8, 0)	/* Pixel Clock Divisor */
2193 #define LCCR3_PixClkDiv(Div)		/* Pixel Clock Divisor */ \
2194 			(((Div) << FShft (LCCR3_PCD)))
2195 
2196 
2197 #define LCCR3_BPP	Fld (3, 24)	/* Bit Per Pixel */
2198 #define LCCR3_Bpp(Bpp)			/* Bit Per Pixel */ \
2199 			((((Bpp&0x7) << FShft (LCCR3_BPP)))|(((Bpp&0x8)<<26)))
2200 
2201 #define LCCR3_ACB	Fld (8, 8)	/* AC Bias */
2202 #define LCCR3_Acb(Acb)			/* BAC Bias */ \
2203 			(((Acb) << FShft (LCCR3_ACB)))
2204 
2205 #define LCCR3_HorSnchH	(LCCR3_HSP*0)	/*  Horizontal Synchronization	   */
2206 					/*  pulse active High		   */
2207 #define LCCR3_HorSnchL	(LCCR3_HSP*1)	/*  Horizontal Synchronization	   */
2208 
2209 #define LCCR3_VrtSnchH	(LCCR3_VSP*0)	/*  Vertical Synchronization pulse */
2210 					/*  active High			   */
2211 #define LCCR3_VrtSnchL	(LCCR3_VSP*1)	/*  Vertical Synchronization pulse */
2212 					/*  active Low			   */
2213 
2214 #define LCSR0_LDD	(1 << 0)	/* LCD Disable Done */
2215 #define LCSR0_SOF	(1 << 1)	/* Start of frame */
2216 #define LCSR0_BER	(1 << 2)	/* Bus error */
2217 #define LCSR0_ABC	(1 << 3)	/* AC Bias count */
2218 #define LCSR0_IUL	(1 << 4)	/* input FIFO underrun Lower panel */
2219 #define LCSR0_IUU	(1 << 5)	/* input FIFO underrun Upper panel */
2220 #define LCSR0_OU	(1 << 6)	/* output FIFO underrun */
2221 #define LCSR0_QD	(1 << 7)	/* quick disable */
2222 #define LCSR0_EOF0	(1 << 8)	/* end of frame */
2223 #define LCSR0_BS	(1 << 9)	/* branch status */
2224 #define LCSR0_SINT	(1 << 10)	/* subsequent interrupt */
2225 
2226 #define LCSR1_SOF1	(1 << 0)
2227 #define LCSR1_SOF2	(1 << 1)
2228 #define LCSR1_SOF3	(1 << 2)
2229 #define LCSR1_SOF4	(1 << 3)
2230 #define LCSR1_SOF5	(1 << 4)
2231 #define LCSR1_SOF6	(1 << 5)
2232 
2233 #define LCSR1_EOF1	(1 << 8)
2234 #define LCSR1_EOF2	(1 << 9)
2235 #define LCSR1_EOF3	(1 << 10)
2236 #define LCSR1_EOF4	(1 << 11)
2237 #define LCSR1_EOF5	(1 << 12)
2238 #define LCSR1_EOF6	(1 << 13)
2239 
2240 #define LCSR1_BS1	(1 << 16)
2241 #define LCSR1_BS2	(1 << 17)
2242 #define LCSR1_BS3	(1 << 18)
2243 #define LCSR1_BS4	(1 << 19)
2244 #define LCSR1_BS5	(1 << 20)
2245 #define LCSR1_BS6	(1 << 21)
2246 
2247 #define LCSR1_IU2	(1 << 25)
2248 #define LCSR1_IU3	(1 << 26)
2249 #define LCSR1_IU4	(1 << 27)
2250 #define LCSR1_IU5	(1 << 28)
2251 #define LCSR1_IU6	(1 << 29)
2252 
2253 #define LDCMD_PAL	(1 << 26)	/* instructs DMA to load palette buffer */
2254 #if defined(CONFIG_CPU_PXA27X)
2255 #define LDCMD_SOFINT	(1 << 22)
2256 #define LDCMD_EOFINT	(1 << 21)
2257 #endif
2258 
2259 /*
2260  * Memory controller
2261  */
2262 
2263 #ifdef CONFIG_CPU_MONAHANS
2264 
2265 /* PXA3xx */
2266 
2267 /* Static Memory Controller Registers */
2268 #define	MSC0		0x4A000008 /* Static Memory Control Register 0 */
2269 #define	MSC1		0x4A00000C /* Static Memory Control Register 1 */
2270 #define	MECR		0x4A000014 /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
2271 #define	SXCNFG		0x4A00001C /* Synchronous Static Memory Control Register */
2272 #define	MCMEM0		0x4A000028 /* Card interface Common Memory Space Socket 0 Timing */
2273 #define	MCATT0		0x4A000030 /* Card interface Attribute Space Socket 0 Timing Configuration */
2274 #define	MCIO0		0x4A000038 /* Card interface I/O Space Socket 0 Timing Configuration */
2275 #define	MEMCLKCFG	0x4A000068 /* SCLK speed configuration */
2276 #define	CSADRCFG0	0x4A000080 /* Address Configuration for chip select 0 */
2277 #define	CSADRCFG1	0x4A000084 /* Address Configuration for chip select 1 */
2278 #define	CSADRCFG2	0x4A000088 /* Address Configuration for chip select 2 */
2279 #define	CSADRCFG3	0x4A00008C /* Address Configuration for chip select 3 */
2280 #define	CSADRCFG_P	0x4A000090 /* Address Configuration for pcmcia card interface */
2281 #define	CSMSADRCFG	0x4A0000A0 /* Master Address Configuration Register */
2282 #define	CLK_RET_DEL	0x4A0000B0 /* Delay line and mux selects for return data latching for sync. flash */
2283 #define	ADV_RET_DEL	0x4A0000B4 /* Delay line and mux selects for return data latching for sync. flash */
2284 
2285 /* Dynamic Memory Controller Registers */
2286 #define	MDCNFG		0x48100000 /* SDRAM Configuration Register 0 */
2287 #define	MDREFR		0x48100004 /* SDRAM Refresh Control Register */
2288 #define	FLYCNFG		0x48100020 /* Fly-by DMA DVAL[1:0] polarities */
2289 #define	MDMRS		0x48100040 /* MRS value to be written to SDRAM */
2290 #define	DDR_SCAL	0x48100050 /* Software Delay Line Calibration/Configuration for external DDR memory. */
2291 #define	DDR_HCAL	0x48100060 /* Hardware Delay Line Calibration/Configuration for external DDR memory. */
2292 #define	DDR_WCAL	0x48100068 /* DDR Write Strobe Calibration Register */
2293 #define	DMCIER		0x48100070 /* Dynamic MC Interrupt Enable Register. */
2294 #define	DMCISR		0x48100078 /* Dynamic MC Interrupt Status Register. */
2295 #define	DDR_DLS		0x48100080 /* DDR Delay Line Value Status register for external DDR memory. */
2296 #define	EMPI		0x48100090 /* EMPI Control Register */
2297 #define	RCOMP		0x48100100
2298 #define	PAD_MA		0x48100110
2299 #define	PAD_MDMSB	0x48100114
2300 #define	PAD_MDLSB	0x48100118
2301 #define	PAD_DMEM	0x4810011c
2302 #define	PAD_SDCLK	0x48100120
2303 #define	PAD_SDCS	0x48100124
2304 #define	PAD_SMEM	0x48100128
2305 #define	PAD_SCLK	0x4810012C
2306 #define	TAI		0x48100F00 /* TAI Tavor Address Isolation Register */
2307 
2308 /* Some frequently used bits */
2309 #define MDCNFG_DMAP	0x80000000	/* SDRAM 1GB Memory Map Enable */
2310 #define MDCNFG_DMCEN	0x40000000	/* Enable Dynamic Memory Controller */
2311 #define MDCNFG_HWFREQ	0x20000000	/* Hardware Frequency Change Calibration */
2312 #define MDCNFG_DTYPE	0x400		/* SDRAM Type: 1=DDR SDRAM */
2313 
2314 #define MDCNFG_DTC_0	0x0		/* Timing Category of SDRAM */
2315 #define MDCNFG_DTC_1	0x100
2316 #define MDCNFG_DTC_2	0x200
2317 #define MDCNFG_DTC_3	0x300
2318 
2319 #define MDCNFG_DRAC_12	0x0		/* Number of Row Access Bits */
2320 #define MDCNFG_DRAC_13	0x20
2321 #define MDCNFG_DRAC_14	0x40
2322 
2323 #define MDCNFG_DCAC_9	0x0		/* Number of Column Acess Bits */
2324 #define MDCNFG_DCAC_10	0x08
2325 #define MDCNFG_DCAC_11	0x10
2326 
2327 #define MDCNFG_DBW_16	0x4		/* SDRAM Data Bus width 16bit */
2328 #define MDCNFG_DCSE1	0x2		/* SDRAM CS 1 Enable */
2329 #define MDCNFG_DCSE0	0x1		/* SDRAM CS 0 Enable */
2330 
2331 
2332 /* Data Flash Controller Registers */
2333 
2334 #define NDCR		0x43100000  /* Data Flash Control register */
2335 #define NDTR0CS0	0x43100004  /* Data Controller Timing Parameter 0 Register for ND_nCS0 */
2336 /* #define NDTR0CS1	0x43100008  /\* Data Controller Timing Parameter 0 Register for ND_nCS1 *\/ */
2337 #define NDTR1CS0	0x4310000C  /* Data Controller Timing Parameter 1 Register for ND_nCS0 */
2338 /* #define NDTR1CS1	0x43100010  /\* Data Controller Timing Parameter 1 Register for ND_nCS1 *\/ */
2339 #define NDSR		0x43100014  /* Data Controller Status Register */
2340 #define NDPCR		0x43100018  /* Data Controller Page Count Register */
2341 #define NDBDR0		0x4310001C  /* Data Controller Bad Block Register 0 */
2342 #define NDBDR1		0x43100020  /* Data Controller Bad Block Register 1 */
2343 #define NDDB		0x43100040  /* Data Controller Data Buffer */
2344 #define NDCB0		0x43100048  /* Data Controller Command Buffer0 */
2345 #define NDCB1		0x4310004C  /* Data Controller Command Buffer1 */
2346 #define NDCB2		0x43100050  /* Data Controller Command Buffer2 */
2347 
2348 #define NDCR_SPARE_EN	(0x1<<31)
2349 #define NDCR_ECC_EN	(0x1<<30)
2350 #define NDCR_DMA_EN	(0x1<<29)
2351 #define NDCR_ND_RUN	(0x1<<28)
2352 #define NDCR_DWIDTH_C	(0x1<<27)
2353 #define NDCR_DWIDTH_M	(0x1<<26)
2354 #define NDCR_PAGE_SZ	(0x3<<24)
2355 #define NDCR_NCSX	(0x1<<23)
2356 #define NDCR_ND_STOP	(0x1<<22)
2357 /* reserved:
2358  * #define NDCR_ND_MODE	(0x3<<21)
2359  * #define NDCR_NAND_MODE   0x0 */
2360 #define NDCR_CLR_PG_CNT	(0x1<<20)
2361 #define NDCR_CLR_ECC	(0x1<<19)
2362 #define NDCR_RD_ID_CNT	(0x7<<16)
2363 #define NDCR_RA_START	(0x1<<15)
2364 #define NDCR_PG_PER_BLK	(0x1<<14)
2365 #define NDCR_ND_ARB_EN	(0x1<<12)
2366 #define NDCR_RDYM	(0x1<<11)
2367 #define NDCR_CS0_PAGEDM	(0x1<<10)
2368 #define NDCR_CS1_PAGEDM	(0x1<<9)
2369 #define NDCR_CS0_CMDDM	(0x1<<8)
2370 #define NDCR_CS1_CMDDM	(0x1<<7)
2371 #define NDCR_CS0_BBDM	(0x1<<6)
2372 #define NDCR_CS1_BBDM	(0x1<<5)
2373 #define NDCR_DBERRM	(0x1<<4)
2374 #define NDCR_SBERRM	(0x1<<3)
2375 #define NDCR_WRDREQM	(0x1<<2)
2376 #define NDCR_RDDREQM	(0x1<<1)
2377 #define NDCR_WRCMDREQM	(0x1)
2378 
2379 #define NDSR_RDY	(0x1<<11)
2380 #define NDSR_CS0_PAGED	(0x1<<10)
2381 #define NDSR_CS1_PAGED	(0x1<<9)
2382 #define NDSR_CS0_CMDD	(0x1<<8)
2383 #define NDSR_CS1_CMDD	(0x1<<7)
2384 #define NDSR_CS0_BBD	(0x1<<6)
2385 #define NDSR_CS1_BBD	(0x1<<5)
2386 #define NDSR_DBERR	(0x1<<4)
2387 #define NDSR_SBERR	(0x1<<3)
2388 #define NDSR_WRDREQ	(0x1<<2)
2389 #define NDSR_RDDREQ	(0x1<<1)
2390 #define NDSR_WRCMDREQ	(0x1)
2391 
2392 #define NDCB0_AUTO_RS	(0x1<<25)
2393 #define NDCB0_CSEL	(0x1<<24)
2394 #define NDCB0_CMD_TYPE	(0x7<<21)
2395 #define NDCB0_NC	(0x1<<20)
2396 #define NDCB0_DBC	(0x1<<19)
2397 #define NDCB0_ADDR_CYC	(0x7<<16)
2398 #define NDCB0_CMD2	(0xff<<8)
2399 #define NDCB0_CMD1	(0xff)
2400 #define MCMEM(s) MCMEM0
2401 #define MCATT(s) MCATT0
2402 #define MCIO(s) MCIO0
2403 #define MECR_CIT	(1 << 1)/* Card Is There: 0 -> no card, 1 -> card inserted */
2404 
2405 /* Maximum values for NAND Interface Timing Registers in DFC clock
2406  * periods */
2407 #define DFC_MAX_tCH	7
2408 #define DFC_MAX_tCS	7
2409 #define DFC_MAX_tWH	7
2410 #define DFC_MAX_tWP	7
2411 #define DFC_MAX_tRH	7
2412 #define DFC_MAX_tRP	15
2413 #define DFC_MAX_tR	65535
2414 #define DFC_MAX_tWHR	15
2415 #define DFC_MAX_tAR	15
2416 
2417 #define DFC_CLOCK	104		/* DFC Clock is 104 MHz */
2418 #define DFC_CLK_PER_US	DFC_CLOCK/1000	/* clock period in ns */
2419 
2420 #else /* CONFIG_CPU_MONAHANS */
2421 
2422 /* PXA2xx */
2423 
2424 #define MEMC_BASE	0x48000000  /* Base of Memory Controller */
2425 #define MDCNFG_OFFSET	0x0
2426 #define MDREFR_OFFSET	0x4
2427 #define MSC0_OFFSET	0x8
2428 #define MSC1_OFFSET	0xC
2429 #define MSC2_OFFSET	0x10
2430 #define MECR_OFFSET	0x14
2431 #define SXLCR_OFFSET	0x18
2432 #define SXCNFG_OFFSET	0x1C
2433 #define FLYCNFG_OFFSET	0x20
2434 #define SXMRS_OFFSET	0x24
2435 #define MCMEM0_OFFSET	0x28
2436 #define MCMEM1_OFFSET	0x2C
2437 #define MCATT0_OFFSET	0x30
2438 #define MCATT1_OFFSET	0x34
2439 #define MCIO0_OFFSET	0x38
2440 #define MCIO1_OFFSET	0x3C
2441 #define MDMRS_OFFSET	0x40
2442 
2443 #define MDCNFG		0x48000000  /* SDRAM Configuration Register 0 */
2444 #define MDCNFG_DE0	0x00000001
2445 #define MDCNFG_DE1	0x00000002
2446 #define MDCNFG_DE2	0x00010000
2447 #define MDCNFG_DE3	0x00020000
2448 #define MDCNFG_DWID0	0x00000004
2449 
2450 #define MDREFR		0x48000004  /* SDRAM Refresh Control Register */
2451 #define MSC0		0x48000008  /* Static Memory Control Register 0 */
2452 #define MSC1		0x4800000C  /* Static Memory Control Register 1 */
2453 #define MSC2		0x48000010  /* Static Memory Control Register 2 */
2454 #define MECR		0x48000014  /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
2455 #define SXLCR		0x48000018  /* LCR value to be written to SDRAM-Timing Synchronous Flash */
2456 #define SXCNFG		0x4800001C  /* Synchronous Static Memory Control Register */
2457 #define FLYCNFG		0x48000020
2458 #define SXMRS		0x48000024  /* MRS value to be written to Synchronous Flash or SMROM */
2459 #define MCMEM0		0x48000028  /* Card interface Common Memory Space Socket 0 Timing */
2460 #define MCMEM1		0x4800002C  /* Card interface Common Memory Space Socket 1 Timing */
2461 #define MCATT0		0x48000030  /* Card interface Attribute Space Socket 0 Timing Configuration */
2462 #define MCATT1		0x48000034  /* Card interface Attribute Space Socket 1 Timing Configuration */
2463 #define MCIO0		0x48000038  /* Card interface I/O Space Socket 0 Timing Configuration */
2464 #define MCIO1		0x4800003C  /* Card interface I/O Space Socket 1 Timing Configuration */
2465 #define MDMRS		0x48000040  /* MRS value to be written to SDRAM */
2466 #define BOOT_DEF	0x48000044  /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
2467 
2468 #define MDREFR_ALTREFA	(1 << 31)	/* Exiting Alternate Bus Master Mode Refresh Control */
2469 #define MDREFR_ALTREFB	(1 << 30)	/* Entering Alternate Bus Master Mode Refresh Control */
2470 #define MDREFR_K0DB4	(1 << 29)	/* SDCLK0 Divide by 4 Control/Status */
2471 #define MDREFR_K2FREE	(1 << 25)	/* SDRAM Free-Running Control */
2472 #define MDREFR_K1FREE	(1 << 24)	/* SDRAM Free-Running Control */
2473 #define MDREFR_K0FREE	(1 << 23)	/* SDRAM Free-Running Control */
2474 #define MDREFR_SLFRSH	(1 << 22)	/* SDRAM Self-Refresh Control/Status */
2475 #define MDREFR_APD	(1 << 20)	/* SDRAM/SSRAM Auto-Power-Down Enable */
2476 #define MDREFR_K2DB2	(1 << 19)	/* SDCLK2 Divide by 2 Control/Status */
2477 #define MDREFR_K2RUN	(1 << 18)	/* SDCLK2 Run Control/Status */
2478 #define MDREFR_K1DB2	(1 << 17)	/* SDCLK1 Divide by 2 Control/Status */
2479 #define MDREFR_K1RUN	(1 << 16)	/* SDCLK1 Run Control/Status */
2480 #define MDREFR_E1PIN	(1 << 15)	/* SDCKE1 Level Control/Status */
2481 #define MDREFR_K0DB2	(1 << 14)	/* SDCLK0 Divide by 2 Control/Status */
2482 #define MDREFR_K0RUN	(1 << 13)	/* SDCLK0 Run Control/Status */
2483 #define MDREFR_E0PIN	(1 << 12)	/* SDCKE0 Level Control/Status */
2484 
2485 #if defined(CONFIG_CPU_PXA27X)
2486 
2487 #define ARB_CNTRL	0x48000048  /* Arbiter Control Register */
2488 
2489 #define ARB_DMA_SLV_PARK	(1<<31)	   /* Be parked with DMA slave when idle */
2490 #define ARB_CI_PARK		(1<<30)	   /* Be parked with Camera Interface when idle */
2491 #define ARB_EX_MEM_PARK		(1<<29)	   /* Be parked with external MEMC when idle */
2492 #define ARB_INT_MEM_PARK	(1<<28)	   /* Be parked with internal MEMC when idle */
2493 #define ARB_USB_PARK		(1<<27)	   /* Be parked with USB when idle */
2494 #define ARB_LCD_PARK		(1<<26)	   /* Be parked with LCD when idle */
2495 #define ARB_DMA_PARK		(1<<25)	   /* Be parked with DMA when idle */
2496 #define ARB_CORE_PARK		(1<<24)	   /* Be parked with core when idle */
2497 #define ARB_LOCK_FLAG		(1<<23)	   /* Only Locking masters gain access to the bus */
2498 
2499 #endif /* CONFIG_CPU_PXA27X */
2500 
2501 /* LCD registers */
2502 #define LCCR4		0x44000010  /* LCD Controller Control Register 4 */
2503 #define LCCR5		0x44000014  /* LCD Controller Control Register 5 */
2504 #define FBR0		0x44000020  /* DMA Channel 0 Frame Branch Register */
2505 #define FBR1		0x44000024  /* DMA Channel 1 Frame Branch Register */
2506 #define FBR2		0x44000028  /* DMA Channel 2 Frame Branch Register */
2507 #define FBR3		0x4400002C  /* DMA Channel 3 Frame Branch Register */
2508 #define FBR4		0x44000030  /* DMA Channel 4 Frame Branch Register */
2509 #define FDADR2		0x44000220  /* DMA Channel 2 Frame Descriptor Address Register */
2510 #define FSADR2		0x44000224  /* DMA Channel 2 Frame Source Address Register */
2511 #define FIDR2		0x44000228  /* DMA Channel 2 Frame ID Register */
2512 #define LDCMD2		0x4400022C  /* DMA Channel 2 Command Register */
2513 #define FDADR3		0x44000230  /* DMA Channel 3 Frame Descriptor Address Register */
2514 #define FSADR3		0x44000234  /* DMA Channel 3 Frame Source Address Register */
2515 #define FIDR3		0x44000238  /* DMA Channel 3 Frame ID Register */
2516 #define LDCMD3		0x4400023C  /* DMA Channel 3 Command Register */
2517 #define FDADR4		0x44000240  /* DMA Channel 4 Frame Descriptor Address Register */
2518 #define FSADR4		0x44000244  /* DMA Channel 4 Frame Source Address Register */
2519 #define FIDR4		0x44000248  /* DMA Channel 4 Frame ID Register */
2520 #define LDCMD4		0x4400024C  /* DMA Channel 4 Command Register */
2521 #define FDADR5		0x44000250  /* DMA Channel 5 Frame Descriptor Address Register */
2522 #define FSADR5		0x44000254  /* DMA Channel 5 Frame Source Address Register */
2523 #define FIDR5		0x44000258  /* DMA Channel 5 Frame ID Register */
2524 #define LDCMD5		0x4400025C  /* DMA Channel 5 Command Register */
2525 
2526 #define OVL1C1		0x44000050  /* Overlay 1 Control Register 1 */
2527 #define OVL1C2		0x44000060  /* Overlay 1 Control Register 2 */
2528 #define OVL2C1		0x44000070  /* Overlay 2 Control Register 1 */
2529 #define OVL2C2		0x44000080  /* Overlay 2 Control Register 2 */
2530 #define CCR		0x44000090  /* Cursor Control Register */
2531 
2532 #define FBR5		0x44000110  /* DMA Channel 5 Frame Branch Register */
2533 #define FBR6		0x44000114  /* DMA Channel 6 Frame Branch Register */
2534 
2535 #define LCCR0_LDDALT	(1<<26)		/* LDD Alternate mapping bit when base pixel is RGBT16 */
2536 #define LCCR0_OUC	(1<<25)		/* Overlay Underlay Control Bit */
2537 
2538 #define LCCR5_SOFM1	(1<<0)		/* Start Of Frame Mask for Overlay 1 (channel 1) */
2539 #define LCCR5_SOFM2	(1<<1)		/* Start Of Frame Mask for Overlay 2 (channel 2) */
2540 #define LCCR5_SOFM3	(1<<2)		/* Start Of Frame Mask for Overlay 2 (channel 3) */
2541 #define LCCR5_SOFM4	(1<<3)		/* Start Of Frame Mask for Overlay 2 (channel 4) */
2542 #define LCCR5_SOFM5	(1<<4)		/* Start Of Frame Mask for cursor (channel 5) */
2543 #define LCCR5_SOFM6	(1<<5)		/* Start Of Frame Mask for command data (channel 6) */
2544 
2545 #define LCCR5_EOFM1	(1<<8)		/* End Of Frame Mask for Overlay 1 (channel 1) */
2546 #define LCCR5_EOFM2	(1<<9)		/* End Of Frame Mask for Overlay 2 (channel 2) */
2547 #define LCCR5_EOFM3	(1<<10)		/* End Of Frame Mask for Overlay 2 (channel 3) */
2548 #define LCCR5_EOFM4	(1<<11)		/* End Of Frame Mask for Overlay 2 (channel 4) */
2549 #define LCCR5_EOFM5	(1<<12)		/* End Of Frame Mask for cursor (channel 5) */
2550 #define LCCR5_EOFM6	(1<<13)		/* End Of Frame Mask for command data (channel 6) */
2551 
2552 #define LCCR5_BSM1	(1<<16)		/* Branch mask for Overlay 1 (channel 1) */
2553 #define LCCR5_BSM2	(1<<17)		/* Branch mask for Overlay 2 (channel 2) */
2554 #define LCCR5_BSM3	(1<<18)		/* Branch mask for Overlay 2 (channel 3) */
2555 #define LCCR5_BSM4	(1<<19)		/* Branch mask for Overlay 2 (channel 4) */
2556 #define LCCR5_BSM5	(1<<20)		/* Branch mask for cursor (channel 5) */
2557 #define LCCR5_BSM6	(1<<21)		/* Branch mask for data command	 (channel 6) */
2558 
2559 #define LCCR5_IUM1	(1<<24)		/* Input FIFO Underrun Mask for Overlay 1  */
2560 #define LCCR5_IUM2	(1<<25)		/* Input FIFO Underrun Mask for Overlay 2  */
2561 #define LCCR5_IUM3	(1<<26)		/* Input FIFO Underrun Mask for Overlay 2  */
2562 #define LCCR5_IUM4	(1<<27)		/* Input FIFO Underrun Mask for Overlay 2  */
2563 #define LCCR5_IUM5	(1<<28)		/* Input FIFO Underrun Mask for cursor */
2564 #define LCCR5_IUM6	(1<<29)		/* Input FIFO Underrun Mask for data command */
2565 
2566 #define OVL1C1_O1EN	(1<<31)		/* Enable bit for Overlay 1 */
2567 #define OVL2C1_O2EN	(1<<31)		/* Enable bit for Overlay 2 */
2568 #define CCR_CEN		(1<<31)		/* Enable bit for Cursor */
2569 
2570 /* Keypad controller */
2571 
2572 #define KPC		0x41500000 /* Keypad Interface Control register */
2573 #define KPDK		0x41500008 /* Keypad Interface Direct Key register */
2574 #define KPREC		0x41500010 /* Keypad Intefcace Rotary Encoder register */
2575 #define KPMK		0x41500018 /* Keypad Intefcace Matrix Key register */
2576 #define KPAS		0x41500020 /* Keypad Interface Automatic Scan register */
2577 #define KPASMKP0	0x41500028 /* Keypad Interface Automatic Scan Multiple Key Presser register 0 */
2578 #define KPASMKP1	0x41500030 /* Keypad Interface Automatic Scan Multiple Key Presser register 1 */
2579 #define KPASMKP2	0x41500038 /* Keypad Interface Automatic Scan Multiple Key Presser register 2 */
2580 #define KPASMKP3	0x41500040 /* Keypad Interface Automatic Scan Multiple Key Presser register 3 */
2581 #define KPKDI		0x41500048 /* Keypad Interface Key Debounce Interval register */
2582 
2583 #define KPC_AS		(0x1 << 30)  /* Automatic Scan bit */
2584 #define KPC_ASACT	(0x1 << 29)  /* Automatic Scan on Activity */
2585 #define KPC_MI		(0x1 << 22)  /* Matrix interrupt bit */
2586 #define KPC_IMKP	(0x1 << 21)  /* Ignore Multiple Key Press */
2587 #define KPC_MS7		(0x1 << 20)  /* Matrix scan line 7 */
2588 #define KPC_MS6		(0x1 << 19)  /* Matrix scan line 6 */
2589 #define KPC_MS5		(0x1 << 18)  /* Matrix scan line 5 */
2590 #define KPC_MS4		(0x1 << 17)  /* Matrix scan line 4 */
2591 #define KPC_MS3		(0x1 << 16)  /* Matrix scan line 3 */
2592 #define KPC_MS2		(0x1 << 15)  /* Matrix scan line 2 */
2593 #define KPC_MS1		(0x1 << 14)  /* Matrix scan line 1 */
2594 #define KPC_MS0		(0x1 << 13)  /* Matrix scan line 0 */
2595 #define KPC_ME		(0x1 << 12)  /* Matrix Keypad Enable */
2596 #define KPC_MIE		(0x1 << 11)  /* Matrix Interrupt Enable */
2597 #define KPC_DK_DEB_SEL	(0x1 <<	 9)  /* Direct Key Debounce select */
2598 #define KPC_DI		(0x1 <<	 5)  /* Direct key interrupt bit */
2599 #define KPC_DEE0	(0x1 <<	 2)  /* Rotary Encoder 0 Enable */
2600 #define KPC_DE		(0x1 <<	 1)  /* Direct Keypad Enable */
2601 #define KPC_DIE		(0x1 <<	 0)  /* Direct Keypad interrupt Enable */
2602 
2603 #define KPDK_DKP	(0x1 << 31)
2604 #define KPDK_DK7	(0x1 <<	 7)
2605 #define KPDK_DK6	(0x1 <<	 6)
2606 #define KPDK_DK5	(0x1 <<	 5)
2607 #define KPDK_DK4	(0x1 <<	 4)
2608 #define KPDK_DK3	(0x1 <<	 3)
2609 #define KPDK_DK2	(0x1 <<	 2)
2610 #define KPDK_DK1	(0x1 <<	 1)
2611 #define KPDK_DK0	(0x1 <<	 0)
2612 
2613 #define KPREC_OF1	(0x1 << 31)
2614 #define kPREC_UF1	(0x1 << 30)
2615 #define KPREC_OF0	(0x1 << 15)
2616 #define KPREC_UF0	(0x1 << 14)
2617 
2618 #define KPMK_MKP	(0x1 << 31)
2619 #define KPAS_SO		(0x1 << 31)
2620 #define KPASMKPx_SO	(0x1 << 31)
2621 
2622 #define GPIO113_BIT	(1 << 17)/* GPIO113 in GPSR, GPCR, bit 17 */
2623 #define PSLR		0x40F00034
2624 #define PSTR		0x40F00038  /* Power Manager Standby Configuration Reg */
2625 #define PSNR		0x40F0003C  /* Power Manager Sense Configuration Reg */
2626 #define PVCR		0x40F00040  /* Power Manager Voltage Change Control Reg */
2627 #define PKWR		0x40F00050  /* Power Manager KB Wake-Up Enable Reg */
2628 #define PKSR		0x40F00054  /* Power Manager KB Level-Detect Status Reg */
2629 #define OSMR4		0x40A00080  /* */
2630 #define OSCR4		0x40A00040  /* OS Timer Counter Register */
2631 #define OMCR4		0x40A000C0  /* */
2632 
2633 #endif	/* CONFIG_CPU_PXA27X */
2634 
2635 #endif	/* _PXA_REGS_H_ */
2636