Searched refs:MDIO (Results 1 – 25 of 27) sorted by relevance
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16 MDIO_DECLARE - Declaration needed to access to the MDIO pin (optional)17 MDIO_ACTIVE - Activate the MDIO pin as out pin18 MDIO_TRISTATE - Activate the MDIO pin as input/tristate pin19 MDIO_READ - Read the MDIO pin20 MDIO(v) - Write v on the MDIO pin37 int (*mdio_active)() - Activate the MDIO pin as output38 int (*mdio_tristate)() - Activate the MDIO pin as input/tristate pin39 int (*set_mdio)() - Write the MDIO pin40 int (*get_mdio)() - Read the MDIO pin
220 mdio - MDIO utility commands
22 connected via the MDIO bus (sometimes the MDIO bus controller is separate).24 * MDIO IO device26 The MDIO is a bus to which the PHY devices are connected. For each45 * TBI Internal MDIO bus48 This PHY is accessed through the local MDIO bus. These buses are defined
24 connected via the MDIO bus (sometimes the MDIO bus controller is separate).
1 * Allwinner A10 MDIO Ethernet Controller interface
5 normal MDIO-managed PHY device. For those situations, a Device Tree
92 /* MDIO */100 /* MDIO reset value */108 /* MDIO via GPIO */128 gpios = <&gpio0 1 GPIO_ACTIVE_HIGH /* MDIO-CLK */129 &gpio0 0 GPIO_ACTIVE_HIGH>; /* MDIO-DATA */
297 /*MDIO*/ &gpio0 14 0>;401 /*MDIO*/ &gpio1 13 0>;505 /*MDIO*/ &gpio0 24 0>;
149 /* MDIO */157 /* MDIO reset value */
245 /* MDIO */253 /* MDIO reset value */
228 /* MDIO */236 /* MDIO reset value */
419 /* MDIO */427 /* MDIO reset value */
462 /* MDIO */470 /* MDIO reset value */
304 /* MDIO */312 /* MDIO reset value */
387 /* MDIO */395 /* MDIO reset value */
278 /* MDIO */286 /* MDIO reset value */
202 "Eth MDIO", "Eth MDC", "Eth RGMII RX Clk",
209 /* MDIO */217 /* MDIO reset value */
181 /* MDIO */189 /* MDIO reset value */
159 bool "Share the MDIO bus for FEC controller"163 hex "MDIO base address for the FEC controller"166 This specifies the MDIO registers base address. It is used when167 two FEC controllers share MDIO bus.
40 #define MDIO 31 macro
315 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ macro
63 MDIO(v); in bb_set_mdio_wrap()
30 write16 PGCR_A, PGCR_D ! SPI0, GETHER MDIO gate(PTG1)
139 If Linux has PHY driver enabled, it still depends on the correct MDIO bus setup