1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2013 Google Inc. 4 * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> 5 * 6 * Modified from coreboot src/soc/intel/baytrail/include/soc/iomap.h 7 */ 8 9 #ifndef _BAYTRAIL_IOMAP_H_ 10 #define _BAYTRAIL_IOMAP_H_ 11 12 /* Memory Mapped IO bases */ 13 14 /* PCI Configuration Space */ 15 #define MCFG_BASE_ADDRESS CONFIG_PCIE_ECAM_BASE 16 #define MCFG_BASE_SIZE 0x10000000 17 18 /* Temporary Base Address */ 19 #define TEMP_BASE_ADDRESS 0xfd000000 20 21 /* Transactions in this range will abort */ 22 #define ABORT_BASE_ADDRESS 0xfeb00000 23 #define ABORT_BASE_SIZE 0x00100000 24 25 /* High Performance Event Timer */ 26 #define HPET_BASE_ADDRESS 0xfed00000 27 #define HPET_BASE_SIZE 0x400 28 29 /* SPI Bus */ 30 #define SPI_BASE_ADDRESS 0xfed01000 31 #define SPI_BASE_SIZE 0x400 32 33 /* Power Management Controller */ 34 #define PMC_BASE_ADDRESS 0xfed03000 35 #define PMC_BASE_SIZE 0x400 36 37 #define GEN_PMCON1 0x20 38 #define UART_EN (1 << 24) 39 #define DISB (1 << 23) 40 #define MEM_SR (1 << 21) 41 #define SRS (1 << 20) 42 #define CTS (1 << 19) 43 #define MS4V (1 << 18) 44 #define PWR_FLR (1 << 16) 45 #define PME_B0_S5_DIS (1 << 15) 46 #define SUS_PWR_FLR (1 << 14) 47 #define WOL_EN_OVRD (1 << 13) 48 #define DIS_SLP_X_STRCH_SUS_UP (1 << 12) 49 #define GEN_RST_STS (1 << 9) 50 #define RPS (1 << 2) 51 #define AFTERG3_EN (1 << 0) 52 #define GEN_PMCON2 0x24 53 #define SLPSX_STR_POL_LOCK (1 << 18) 54 #define BIOS_PCI_EXP_EN (1 << 10) 55 #define PWRBTN_LVL (1 << 9) 56 #define SMI_LOCK (1 << 4) 57 58 /* Power Management Unit */ 59 #define PUNIT_BASE_ADDRESS 0xfed05000 60 #define PUNIT_BASE_SIZE 0x800 61 62 /* Intel Legacy Block */ 63 #define ILB_BASE_ADDRESS 0xfed08000 64 #define ILB_BASE_SIZE 0x400 65 66 /* IO Memory */ 67 #define IO_BASE_ADDRESS 0xfed0c000 68 #define IO_BASE_OFFSET_GPSCORE 0x0000 69 #define IO_BASE_OFFSET_GPNCORE 0x1000 70 #define IO_BASE_OFFSET_GPSSUS 0x2000 71 #define IO_BASE_SIZE 0x4000 72 73 /* Root Complex Base Address */ 74 #define RCBA_BASE_ADDRESS 0xfed1c000 75 #define RCBA_BASE_SIZE 0x400 76 77 /* MODPHY */ 78 #define MPHY_BASE_ADDRESS 0xfef00000 79 #define MPHY_BASE_SIZE 0x100000 80 81 /* IO Port bases */ 82 #define ACPI_BASE_ADDRESS 0x0400 83 #define ACPI_BASE_SIZE 0x80 84 85 #define PM1_STS 0x00 86 #define PM1_CNT 0x04 87 88 #define GPIO_BASE_ADDRESS 0x0500 89 #define GPIO_BASE_SIZE 0x100 90 91 #define SMBUS_BASE_ADDRESS 0xefa0 92 93 #endif /* _BAYTRAIL_IOMAP_H_ */ 94