| /external/v8/src/compiler/mips64/ |
| D | instruction-scheduler-mips64.cc | 450 MFHI = 1, enumerator
514 latency = Latency::MULT + Latency::MFHI; in MulhLatency()
527 latency = Latency::MULTU + Latency::MFHI; in MulhuLatency()
540 latency = Latency::DMULT + Latency::MFHI; in DMulhLatency()
595 latency = Latency::DIV + Latency::MFHI; in ModLatency()
608 latency = Latency::DIVU + Latency::MFHI; in ModuLatency()
621 latency = Latency::DDIV + Latency::MFHI; in DmodLatency()
634 latency = Latency::DDIV + Latency::MFHI; in DmoduLatency()
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| /external/v8/src/compiler/mips/ |
| D | instruction-scheduler-mips.cc | 419 MFHI = 1, enumerator
968 return Latency::MULT + Latency::MFHI; in MulhLatency()
974 return 1 + Latency::MULT + Latency::MFHI; in MulhLatency()
984 return Latency::MULTU + Latency::MFHI; in MulhuLatency()
990 return 1 + Latency::MULTU + Latency::MFHI; in MulhuLatency()
1004 return Latency::DIV + Latency::MFHI; in ModLatency()
1010 return 1 + Latency::DIV + Latency::MFHI; in ModLatency()
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| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsISelDAGToDAG.cpp | 257 SDNode *Hi = CurDAG->getMachineNode(Mips::MFHI, dl, MVT::i32, InFlag); in Select()
294 return CurDAG->getMachineNode(Mips::MFHI, dl, MVT::i32, InFlag); in Select()
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| D | MipsInstrInfo.cpp | 116 Opc = Mips::MFHI, SrcReg = 0; in copyPhysReg()
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| D | MipsInstrInfo.td | 757 def MFHI : MoveFromLOHI<0x10, "mfhi">;
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 97 Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI; in copyPhysReg()
232 BuildMI(MBB, I, DL, get(Mips::MFHI), Mips::K0); in storeRegToStack()
346 Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI; in expandPostRAPseudo()
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| D | MipsDSPInstrFormats.td | 254 // MFHI sub-class format.
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| D | MipsISelLowering.h | 77 MFHI, enumerator
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| D | MipsSEISelLowering.cpp | 449 SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MAdd); in selectMADD()
521 SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MSub); in selectMSUB()
1286 Hi = DAG.getNode(MipsISD::MFHI, DL, Ty, Mult); in lowerMulDiv()
1305 SDValue Hi = DAG.getNode(MipsISD::MFHI, DL, MVT::i32, Op); in extractLOHI()
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| D | MipsSEFrameLowering.cpp | 800 Op = (Reg == Mips::HI0) ? Mips::MFHI : Mips::MFLO; in spillCalleeSavedRegisters()
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| D | MipsFastISel.cpp | 1697 ? Mips::MFHI in selectDivRem()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 102 Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI; in copyPhysReg()
305 BuildMI(MBB, I, DL, get(Mips::MFHI), Mips::K0); in storeRegToStack()
424 Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI; in expandPostRAPseudo()
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| D | MipsDSPInstrFormats.td | 254 // MFHI sub-class format.
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| D | MipsISelLowering.h | 128 MFHI, enumerator
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| D | MipsSEFrameLowering.cpp | 823 Op = (Reg == Mips::HI0) ? Mips::MFHI : Mips::MFLO; in spillCalleeSavedRegisters()
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| D | MipsScheduleP5600.td | 169 def : InstRW<[P5600WriteAL2], (instrs CLO, CLZ, DI, EI, MFHI, MFLO,
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| D | MipsSEISelLowering.cpp | 1239 Hi = DAG.getNode(MipsISD::MFHI, DL, Ty, Mult); in lowerMulDiv()
1258 SDValue Hi = DAG.getNode(MipsISD::MFHI, DL, MVT::i32, Op); in extractLOHI()
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| /external/v8/src/mips/ |
| D | constants-mips.h | 515 MFHI = ((2U << 3) + 0), enumerator
1286 FunctionFieldToBitNumber(MFHI) | FunctionFieldToBitNumber(MFLO) |
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| D | disasm-mips.cc | 1336 case MFHI: in DecodeTypeRegisterSPECIAL()
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| /external/v8/src/mips64/ |
| D | constants-mips64.h | 497 MFHI = ((2U << 3) + 0), enumerator
1328 FunctionFieldToBitNumber(MFHI) | FunctionFieldToBitNumber(MFLO) |
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| D | disasm-mips64.cc | 1519 case MFHI: in DecodeTypeRegisterSPECIAL()
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| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeMIPS_common.c | 159 #define MFHI (HI(0) | LO(16)) macro
1084 return push_inst(compiler, MFHI | D(SLJIT_R1), DR(SLJIT_R1)); in sljit_emit_op0()
1105 …return (op >= SLJIT_DIV_UW) ? SLJIT_SUCCESS : push_inst(compiler, MFHI | D(SLJIT_R1), DR(SLJIT_R1)… in sljit_emit_op0()
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| D | sljitNativeMIPS_32.c | 379 FAIL_IF(push_inst(compiler, MFHI | DA(EQUAL_FLAG), EQUAL_FLAG)); in emit_single_op()
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| D | sljitNativeMIPS_64.c | 473 FAIL_IF(push_inst(compiler, MFHI | DA(EQUAL_FLAG), EQUAL_FLAG)); in emit_single_op()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 4015 TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI); in expandDivRem()
4064 TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI); in expandDivRem()
4102 TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI); in expandDivRem()
4751 TOut.emitR(Mips::MFHI, ATReg, IDLoc, STI); in expandMulO()
4788 TOut.emitR(Mips::MFHI, ATReg, IDLoc, STI); in expandMulOU()
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