| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64CollectLOH.cpp | 284 const MachineInstr *MI1; ///< Second instruction involved in the LOH member
311 Info.MI1 = nullptr; in handleUse()
352 OpInfo.MI1 = &MI; in handleMiddleInst()
354 } else if (OpInfo.Type == MCLOH_AdrpAddStr && OpInfo.MI1 == nullptr) { in handleMiddleInst()
357 OpInfo.MI1 = &MI; in handleMiddleInst()
364 if (OpInfo.Type == MCLOH_AdrpAddStr && OpInfo.MI1 == nullptr) { in handleMiddleInst()
367 OpInfo.MI1 = &MI; in handleMiddleInst()
372 OpInfo.MI1 = &MI; in handleMiddleInst()
408 << '\t' << MI << '\t' << *Info.MI1 << '\t' in handleADRP()
410 AFI.addLOHDirective(MCLOH_AdrpAddLdr, {&MI, Info.MI1, Info.MI0}); in handleADRP()
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| /external/swiftshader/third_party/llvm-7.0/llvm/unittests/CodeGen/ |
| D | MachineInstrTest.cpp | 120 auto MI1 = MF->CreateMachineInstr(MCID, DebugLoc()); in TEST() local
121 MI1->addOperand(*MF, MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true)); in TEST()
122 MI1->addOperand(*MF, MachineOperand::CreateReg(VirtualUse, /*isDef*/ false)); in TEST()
130 ASSERT_FALSE(MI1->isIdenticalTo(*MI2, MachineInstr::CheckDefs)); in TEST()
131 ASSERT_FALSE(MI2->isIdenticalTo(*MI1, MachineInstr::CheckDefs)); in TEST()
133 ASSERT_TRUE(MI1->isIdenticalTo(*MI2, MachineInstr::IgnoreVRegDefs)); in TEST()
134 ASSERT_TRUE(MI2->isIdenticalTo(*MI1, MachineInstr::IgnoreVRegDefs)); in TEST()
158 void checkHashAndIsEqualMatch(MachineInstr *MI1, MachineInstr *MI2) { in checkHashAndIsEqualMatch() argument
159 bool IsEqual1 = MachineInstrExpressionTrait::isEqual(MI1, MI2); in checkHashAndIsEqualMatch()
160 bool IsEqual2 = MachineInstrExpressionTrait::isEqual(MI2, MI1); in checkHashAndIsEqualMatch()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIFixSGPRCopies.cpp | 477 MachineInstr *MI1 = *I1; in hoistAndMergeSGPRInits() local
515 if (MDT.dominates(MI1, MI2)) { in hoistAndMergeSGPRInits()
516 if (!intereferes(MI2, MI1)) { in hoistAndMergeSGPRInits()
525 } else if (MDT.dominates(MI2, MI1)) { in hoistAndMergeSGPRInits()
526 if (!intereferes(MI1, MI2)) { in hoistAndMergeSGPRInits()
529 << printMBBReference(*MI1->getParent()) << " " << *MI1); in hoistAndMergeSGPRInits()
530 MI1->eraseFromParent(); in hoistAndMergeSGPRInits()
536 auto *MBB = MDT.findNearestCommonDominator(MI1->getParent(), in hoistAndMergeSGPRInits()
544 if (!intereferes(MI1, I) && !intereferes(MI2, I)) { in hoistAndMergeSGPRInits()
547 << printMBBReference(*MI1->getParent()) << " " << *MI1 in hoistAndMergeSGPRInits()
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| D | AMDGPUSubtarget.cpp | 651 MachineInstr &MI1 = *SUa->getInstr(); in apply() local
652 if ((TII->isVMEM(MI1) && TII->isVMEM(MI2)) || in apply()
653 (TII->isFLAT(MI1) && TII->isFLAT(MI2)) || in apply()
654 (TII->isSMRD(MI1) && TII->isSMRD(MI2)) || in apply()
655 (TII->isDS(MI1) && TII->isDS(MI2))) { in apply()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MicroMipsSizeReduction.cpp | 392 static bool ConsecutiveInstr(MachineInstr *MI1, MachineInstr *MI2) { in ConsecutiveInstr() argument
395 if (!GetImm(MI1, 2, Offset1)) in ConsecutiveInstr()
400 unsigned Reg1 = MI1->getOperand(0).getReg(); in ConsecutiveInstr()
458 MachineInstr *MI1 = Arguments->MI; in ReduceXWtoXWP() local
462 bool ReduceToLwp = (MI1->getOpcode() == Mips::LW) || in ReduceXWtoXWP()
463 (MI1->getOpcode() == Mips::LW_MM) || in ReduceXWtoXWP()
464 (MI1->getOpcode() == Mips::LW16_MM); in ReduceXWtoXWP()
466 if (!CheckXWPInstr(MI1, ReduceToLwp, Entry)) in ReduceXWtoXWP()
472 unsigned Reg1 = MI1->getOperand(1).getReg(); in ReduceXWtoXWP()
478 bool ConsecutiveForward = ConsecutiveInstr(MI1, MI2); in ReduceXWtoXWP()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | TargetInstrInfo.cpp | 422 const MachineInstr &MI1, in produceSameValue() argument
424 return MI0.isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs); in produceSameValue()
678 MachineInstr *MI1 = nullptr; in hasReassociableOperands() local
681 MI1 = MRI.getUniqueVRegDef(Op1.getReg()); in hasReassociableOperands()
686 return MI1 && MI2 && MI1->getParent() == MBB && MI2->getParent() == MBB; in hasReassociableOperands()
693 MachineInstr *MI1 = MRI.getUniqueVRegDef(Inst.getOperand(1).getReg()); in hasReassociableSibling() local
699 Commuted = MI1->getOpcode() != AssocOpcode && MI2->getOpcode() == AssocOpcode; in hasReassociableSibling()
701 std::swap(MI1, MI2); in hasReassociableSibling()
707 return MI1->getOpcode() == AssocOpcode && in hasReassociableSibling()
708 hasReassociableOperands(*MI1, MBB) && in hasReassociableSibling()
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| D | DFAPacketizer.cpp | 360 bool VLIWPacketizerList::alias(const MachineInstr &MI1, in alias() argument
363 if (MI1.memoperands_empty() || MI2.memoperands_empty()) in alias()
366 for (const MachineMemOperand *Op1 : MI1.memoperands()) in alias()
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| /external/llvm/lib/CodeGen/ |
| D | TargetInstrInfo.cpp | 386 const MachineInstr &MI1, in produceSameValue() argument
388 return MI0.isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs); in produceSameValue()
570 MachineInstr *MI1 = nullptr; in hasReassociableOperands() local
573 MI1 = MRI.getUniqueVRegDef(Op1.getReg()); in hasReassociableOperands()
578 return MI1 && MI2 && MI1->getParent() == MBB && MI2->getParent() == MBB; in hasReassociableOperands()
585 MachineInstr *MI1 = MRI.getUniqueVRegDef(Inst.getOperand(1).getReg()); in hasReassociableSibling() local
591 Commuted = MI1->getOpcode() != AssocOpcode && MI2->getOpcode() == AssocOpcode; in hasReassociableSibling()
593 std::swap(MI1, MI2); in hasReassociableSibling()
599 return MI1->getOpcode() == AssocOpcode && in hasReassociableSibling()
600 hasReassociableOperands(*MI1, MBB) && in hasReassociableSibling()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonSubtarget.cpp | 147 MachineInstr &MI1 = *SU.getInstr(); in apply() local
149 bool IsStoreMI1 = MI1.mayStore(); in apply()
150 bool IsLoadMI1 = MI1.mayLoad(); in apply()
151 if (!QII->isHVXVec(MI1) || !(IsStoreMI1 || IsLoadMI1)) in apply()
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| D | HexagonVLIWPacketizer.cpp | 960 bool HexagonPacketizerList::arePredicatesComplements(MachineInstr &MI1, in arePredicatesComplements() argument
964 if (getPredicateSense(MI1, HII) == PK_Unknown || in arePredicatesComplements()
969 SUnit *SU = MIToSUnit[&MI1]; in arePredicatesComplements()
1017 unsigned PReg1 = getPredicatedRegister(MI1, HII); in arePredicatesComplements()
1022 getPredicateSense(MI1, HII) != getPredicateSense(MI2, HII) && in arePredicatesComplements()
1023 HII->isDotNewInst(MI1) == HII->isDotNewInst(MI2); in arePredicatesComplements()
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| D | HexagonInstrInfo.h | 407 bool isToBeScheduledASAP(const MachineInstr &MI1,
419 bool addLatencyToSchedule(const MachineInstr &MI1,
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| D | HexagonVLIWPacketizer.h | 134 bool arePredicatesComplements(MachineInstr &MI1, MachineInstr &MI2);
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonVLIWPacketizer.cpp | 844 bool HexagonPacketizerList::arePredicatesComplements(MachineInstr &MI1, in arePredicatesComplements() argument
848 if (getPredicateSense(MI1, HII) == PK_Unknown || in arePredicatesComplements()
853 SUnit *SU = MIToSUnit[&MI1]; in arePredicatesComplements()
901 unsigned PReg1 = getPredicatedRegister(MI1, HII); in arePredicatesComplements()
906 getPredicateSense(MI1, HII) != getPredicateSense(MI2, HII) && in arePredicatesComplements()
907 HII->isDotNewInst(&MI1) == HII->isDotNewInst(&MI2); in arePredicatesComplements()
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| D | HexagonVLIWPacketizer.h | 97 bool arePredicatesComplements(MachineInstr &MI1, MachineInstr &MI2);
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | MLxExpansionPass.cpp | 251 MachineInstr &MI1 = *MII; in ExpandFPMLxInstruction()
252 dbgs() << " " << MI1; in ExpandFPMLxInstruction()
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| D | ARMBaseInstrInfo.cpp | 1164 const MachineInstr *MI1, in produceSameValue() argument
1176 if (MI1->getOpcode() != Opcode) in produceSameValue()
1178 if (MI0->getNumOperands() != MI1->getNumOperands()) in produceSameValue()
1182 const MachineOperand &MO1 = MI1->getOperand(1); in produceSameValue()
1213 if (MI1->getOpcode() != Opcode) in produceSameValue()
1215 if (MI0->getNumOperands() != MI1->getNumOperands()) in produceSameValue()
1219 unsigned Addr1 = MI1->getOperand(1).getReg(); in produceSameValue()
1238 const MachineOperand &MO1 = MI1->getOperand(i); in produceSameValue()
1245 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs); in produceSameValue()
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| D | ARMBaseInstrInfo.h | 143 const MachineInstr *MI1,
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| /external/llvm/lib/Target/X86/ |
| D | X86OptimizeLEAs.cpp | 249 int64_t getAddrDispShift(const MachineInstr &MI1, unsigned N1,
364 int64_t OptimizeLEAPass::getAddrDispShift(const MachineInstr &MI1, unsigned N1, in getAddrDispShift() argument
367 const MachineOperand &Op1 = MI1.getOperand(N1 + X86::AddrDisp); in getAddrDispShift()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86OptimizeLEAs.cpp | 268 int64_t getAddrDispShift(const MachineInstr &MI1, unsigned N1,
391 int64_t OptimizeLEAPass::getAddrDispShift(const MachineInstr &MI1, unsigned N1, in getAddrDispShift() argument
394 const MachineOperand &Op1 = MI1.getOperand(N1 + X86::AddrDisp); in getAddrDispShift()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | DFAPacketizer.h | 212 bool alias(const MachineInstr &MI1, const MachineInstr &MI2,
|
| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetInstrInfo.h | 242 const MachineInstr *MI1,
759 const MachineInstr *MI1,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | MLxExpansionPass.cpp | 319 MachineInstr &MI1 = *MII; in ExpandFPMLxInstruction()
320 dbgs() << " " << MI1; in ExpandFPMLxInstruction()
|
| /external/llvm/lib/Target/ARM/ |
| D | MLxExpansionPass.cpp | 319 MachineInstr &MI1 = *MII; in ExpandFPMLxInstruction()
320 dbgs() << " " << MI1; in ExpandFPMLxInstruction()
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| D | ARMBaseInstrInfo.cpp | 1451 const MachineInstr &MI1, in produceSameValue() argument
1464 if (MI1.getOpcode() != Opcode) in produceSameValue()
1466 if (MI0.getNumOperands() != MI1.getNumOperands()) in produceSameValue()
1470 const MachineOperand &MO1 = MI1.getOperand(1); in produceSameValue()
1502 if (MI1.getOpcode() != Opcode) in produceSameValue()
1504 if (MI0.getNumOperands() != MI1.getNumOperands()) in produceSameValue()
1508 unsigned Addr1 = MI1.getOperand(1).getReg(); in produceSameValue()
1527 const MachineOperand &MO1 = MI1.getOperand(i); in produceSameValue()
1534 return MI0.isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs); in produceSameValue()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | TargetInstrInfoImpl.cpp | 214 const MachineInstr *MI1, in produceSameValue() argument
216 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs); in produceSameValue()
|