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Searched refs:MID (Results 1 – 25 of 46) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Darm64-convert-v4f64.ll8 ; CHECK-DAG: xtn v[[MID:[0-9]+]].2s, v[[LHS]].2d
9 ; CHECK-DAG: xtn2 v[[MID]].4s, v[[RHS]].2d
10 ; CHECK: xtn v0.4h, v[[MID]].4s
38 ; CHECK-DAG: fcvtn v[[MID:[0-9]+]].2s, v[[LHS]].2d
39 ; CHECK-DAG: fcvtn2 v[[MID]].4s, v[[RHS]].2d
40 ; CHECK: fcvtn v0.4h, v[[MID]].4s
60 ; CHECK-DAG: xtn v[[MID:[0-9]+]].2s, v[[LHS]].2d
61 ; CHECK-DAG: xtn2 v[[MID]].4s, v[[RHS]].2d
62 ; CHECK: xtn v0.4h, v[[MID]].4s
/external/llvm/test/CodeGen/AArch64/
Darm64-convert-v4f64.ll8 ; CHECK-DAG: xtn v[[MID:[0-9]+]].2s, v[[LHS]].2d
9 ; CHECK-DAG: xtn2 v[[MID]].4s, v[[RHS]].2d
10 ; CHECK: xtn v0.4h, v[[MID]].4s
38 ; CHECK-DAG: fcvtn v[[MID:[0-9]+]].2s, v[[LHS]].2d
39 ; CHECK-DAG: fcvtn2 v[[MID]].4s, v[[RHS]].2d
40 ; CHECK: fcvtn v0.4h, v[[MID]].4s
60 ; CHECK-DAG: xtn v[[MID:[0-9]+]].2s, v[[LHS]].2d
61 ; CHECK-DAG: xtn2 v[[MID]].4s, v[[RHS]].2d
62 ; CHECK: xtn v0.4h, v[[MID]].4s
/external/llvm/lib/CodeGen/
DDFAPacketizer.cpp119 bool DFAPacketizer::canReserveResources(const llvm::MCInstrDesc *MID) { in canReserveResources() argument
120 unsigned InsnClass = MID->getSchedClass(); in canReserveResources()
130 void DFAPacketizer::reserveResources(const llvm::MCInstrDesc *MID) { in reserveResources() argument
131 unsigned InsnClass = MID->getSchedClass(); in reserveResources()
143 const llvm::MCInstrDesc &MID = MI.getDesc(); in canReserveResources() local
144 return canReserveResources(&MID); in canReserveResources()
151 const llvm::MCInstrDesc &MID = MI.getDesc(); in reserveResources() local
152 reserveResources(&MID); in reserveResources()
DMachineLICM.cpp1172 const MCInstrDesc &MID = TII->get(NewOpc); in ExtractHoistableLoad() local
1174 const TargetRegisterClass *RC = TII->getRegClass(MID, LoadRegIndex, TRI, MF); in ExtractHoistableLoad()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DDFAPacketizer.cpp130 bool DFAPacketizer::canReserveResources(const MCInstrDesc *MID) { in canReserveResources() argument
131 unsigned InsnClass = MID->getSchedClass(); in canReserveResources()
140 void DFAPacketizer::reserveResources(const MCInstrDesc *MID) { in reserveResources() argument
141 unsigned InsnClass = MID->getSchedClass(); in reserveResources()
152 const MCInstrDesc &MID = MI.getDesc(); in canReserveResources() local
153 return canReserveResources(&MID); in canReserveResources()
159 const MCInstrDesc &MID = MI.getDesc(); in reserveResources() local
160 reserveResources(&MID); in reserveResources()
DMachineLICM.cpp1302 const MCInstrDesc &MID = TII->get(NewOpc); in ExtractHoistableLoad() local
1304 const TargetRegisterClass *RC = TII->getRegClass(MID, LoadRegIndex, TRI, MF); in ExtractHoistableLoad()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonOptAddrMode.cpp127 const MCInstrDesc &MID = MI.getDesc(); in INITIALIZE_PASS_DEPENDENCY() local
129 if ((!MID.mayStore() && !MID.mayLoad()) || HII->isPredicated(MI)) in INITIALIZE_PASS_DEPENDENCY()
132 if (MID.mayStore()) { in INITIALIZE_PASS_DEPENDENCY()
357 const MCInstrDesc &MID = MI->getDesc(); in processAddUses() local
358 if ((!MID.mayLoad() && !MID.mayStore()) || in processAddUses()
363 MachineOperand BaseOp = MID.mayLoad() ? MI->getOperand(1) in processAddUses()
369 MachineOperand OffsetOp = MID.mayLoad() ? MI->getOperand(2) in processAddUses()
416 const MCInstrDesc &MID = UseMI->getDesc(); in updateAddUses() local
418 MachineOperand &BaseOp = MID.mayLoad() ? UseMI->getOperand(1) in updateAddUses()
420 MachineOperand &OffsetOp = MID.mayLoad() ? UseMI->getOperand(2) in updateAddUses()
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonOptAddrMode.cpp108 const MCInstrDesc &MID = MI->getDesc(); in INITIALIZE_PASS_DEPENDENCY() local
110 if ((!MID.mayStore() && !MID.mayLoad()) || HII->isPredicated(*MI)) in INITIALIZE_PASS_DEPENDENCY()
113 if (MID.mayStore()) { in INITIALIZE_PASS_DEPENDENCY()
265 const MCInstrDesc &MID = MI->getDesc(); in analyzeUses() local
266 if ((MID.mayLoad() || MID.mayStore())) { in analyzeUses()
491 const MCInstrDesc &MID = UseMI->getDesc(); in xformUseMI() local
493 if (MID.mayLoad()) in xformUseMI()
495 else if (MID.mayStore()) in xformUseMI()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/
DSystemZHazardRecognizer.cpp121 const MCInstrDesc &MID = MI->getDesc(); in has4RegOps() local
123 for (unsigned OpIdx = 0; OpIdx < MID.getNumOperands(); OpIdx++) { in has4RegOps()
124 const TargetRegisterClass *RC = TII->getRegClass(MID, OpIdx, TRI, MF); in has4RegOps()
127 if (OpIdx >= MID.getNumDefs() && in has4RegOps()
128 MID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) in has4RegOps()
/external/llvm/include/llvm/CodeGen/
DDFAPacketizer.h104 bool canReserveResources(const llvm::MCInstrDesc *MID);
108 void reserveResources(const llvm::MCInstrDesc *MID);
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DDFAPacketizer.h110 bool canReserveResources(const MCInstrDesc *MID);
114 void reserveResources(const MCInstrDesc *MID);
/external/swiftshader/third_party/llvm-7.0/llvm/lib/IR/
DModule.cpp72 Module::Module(StringRef MID, LLVMContext &C) in Module() argument
73 : Context(C), Materializer(), ModuleID(MID), SourceFileName(MID), DL("") { in Module()
/external/llvm/lib/IR/
DModule.cpp51 Module::Module(StringRef MID, LLVMContext &C) in Module() argument
52 : Context(C), Materializer(), ModuleID(MID), SourceFileName(MID), DL("") { in Module()
/external/bcc/introspection/
Dbps_example.txt18 MID TYPE FLAGS KeySz ValueSz MaxEnts NAME
/external/libcxx/test/libcxx/utilities/function.objects/func.require/
Dbullet_7.pass.cpp174 typedef MethodID<CallSig ClassType::*> MID; in run() typedef
175 BasicTest<MID, Arity, ObjCaster, ArgCaster> t; in run()
/external/swiftshader/third_party/LLVM/lib/VMCore/
DModule.cpp45 Module::Module(StringRef MID, LLVMContext& C) in Module() argument
46 : Context(C), Materializer(NULL), ModuleID(MID) { in Module()
/external/llvm/lib/Transforms/Scalar/
DLoopDistribute.cpp644 MemoryInstructionDependences MID(DepChecker.getMemoryInstructions(), in processLoop() local
648 for (auto &InstDep : MID) { in processLoop()
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DMachineLICM.cpp1107 const MCInstrDesc &MID = TII->get(NewOpc); in ExtractHoistableLoad() local
1108 if (MID.getNumDefs() != 1) return 0; in ExtractHoistableLoad()
1109 const TargetRegisterClass *RC = TII->getRegClass(MID, LoadRegIndex, TRI); in ExtractHoistableLoad()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/Scalar/
DLoopDistribute.cpp684 MemoryInstructionDependences MID(DepChecker.getMemoryInstructions(), in processLoop() local
688 for (auto &InstDep : MID) { in processLoop()
/external/clang/lib/Frontend/
DASTUnit.cpp1203 llvm::sys::fs::UniqueID MID; in ComputePreamble() local
1204 if (!llvm::sys::fs::getUniqueID(MPath, MID)) { in ComputePreamble()
1205 if (MainFileID == MID) { in ComputePreamble()
1218 llvm::sys::fs::UniqueID MID; in ComputePreamble() local
1219 if (!llvm::sys::fs::getUniqueID(MPath, MID)) { in ComputePreamble()
1220 if (MainFileID == MID) { in ComputePreamble()
/external/u-boot/arch/x86/
DKconfig85 bool "Intel MID platform support"
89 Select to build a U-Boot capable of supporting Intel MID
95 Intel MID platforms are based on an Intel processor and
/external/swiftshader/third_party/LLVM/lib/AsmParser/
DLLParser.cpp471 unsigned MID = 0; in ParseMDNodeID() local
472 if (ParseMDNodeID(Result, MID)) return true; in ParseMDNodeID()
479 ForwardRefMDNodes[MID] = std::make_pair(FwdNode, Lex.getLoc()); in ParseMDNodeID()
481 if (NumberedMetadata.size() <= MID) in ParseMDNodeID()
482 NumberedMetadata.resize(MID+1); in ParseMDNodeID()
483 NumberedMetadata[MID] = FwdNode; in ParseMDNodeID()
/external/cldr/tools/java/org/unicode/cldr/draft/
DScriptData.txt77 U+02E7 ( ˧ ) MODIFIER LETTER MID TONE BAR
99 U+A70A ( ꜊ ) MODIFIER LETTER MID DOTTED TONE BAR
104 U+A70F ( ꜏ ) MODIFIER LETTER MID DOTTED LEFT-STEM TONE BAR
110 U+A714 ( ꜔ ) MODIFIER LETTER MID LEFT-STEM TONE BAR
/external/u-boot/drivers/serial/
DKconfig534 bool "Intel MID platform UART support"
539 Select this to enable a UART for Intel MID platforms.
/external/u-boot/drivers/net/
Dmacb.c146 return MACB_BFEXT(IDNUM, macb_readl(macb, MID)) == 0x2; in macb_is_gem()

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