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Searched refs:MI_FLUSH_DW (Results 1 – 5 of 5) sorted by relevance

/external/libdrm/intel/tests/
Dgen7-2d-copy.batch-ref.txt9 0x12300020: 0x13000002: MI_FLUSH_DW post_sync_op='no write'
/external/mesa3d/src/mesa/drivers/dri/i915/
Dintel_reg.h42 #define MI_FLUSH_DW (CMD_MI | (0x26 << 23) | 2) macro
/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_pipe_control.c542 OUT_BATCH(MI_FLUSH_DW | (n_dwords - 2)); in brw_emit_mi_flush()
Dintel_blit.c109 OUT_BATCH(MI_FLUSH_DW | (n_dwords - 2)); in set_blitter_tiling()
Dbrw_defines.h1433 #define MI_FLUSH_DW (CMD_MI | (0x26 << 23)) macro