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1 /*
2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
3  Intel funded Tungsten Graphics to
4  develop this 3D driver.
5 
6  Permission is hereby granted, free of charge, to any person obtaining
7  a copy of this software and associated documentation files (the
8  "Software"), to deal in the Software without restriction, including
9  without limitation the rights to use, copy, modify, merge, publish,
10  distribute, sublicense, and/or sell copies of the Software, and to
11  permit persons to whom the Software is furnished to do so, subject to
12  the following conditions:
13 
14  The above copyright notice and this permission notice (including the
15  next paragraph) shall be included in all copies or substantial
16  portions of the Software.
17 
18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 
26  **********************************************************************/
27  /*
28   * Authors:
29   *   Keith Whitwell <keithw@vmware.com>
30   */
31 
32 #ifndef BRW_DEFINES_H
33 #define BRW_DEFINES_H
34 
35 #include "util/macros.h"
36 
37 #define INTEL_MASK(high, low) (((1u<<((high)-(low)+1))-1)<<(low))
38 /* Using the GNU statement expression extension */
39 #define SET_FIELD(value, field)                                         \
40    ({                                                                   \
41       uint32_t fieldval = (value) << field ## _SHIFT;                   \
42       assert((fieldval & ~ field ## _MASK) == 0);                       \
43       fieldval & field ## _MASK;                                        \
44    })
45 
46 #define GET_BITS(data, high, low) ((data & INTEL_MASK((high), (low))) >> (low))
47 #define GET_FIELD(word, field) (((word)  & field ## _MASK) >> field ## _SHIFT)
48 
49 /**
50  * For use with masked MMIO registers where the upper 16 bits control which
51  * of the lower bits are committed to the register.
52  */
53 #define REG_MASK(value) ((value) << 16)
54 
55 /* 3D state:
56  */
57 #define CMD_3D_PRIM                                 0x7b00 /* 3DPRIMITIVE */
58 /* DW0 */
59 # define GEN4_3DPRIM_TOPOLOGY_TYPE_SHIFT            10
60 # define GEN4_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL (0 << 15)
61 # define GEN4_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM     (1 << 15)
62 # define GEN7_3DPRIM_INDIRECT_PARAMETER_ENABLE      (1 << 10)
63 # define GEN7_3DPRIM_PREDICATE_ENABLE               (1 << 8)
64 /* DW1 */
65 # define GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL (0 << 8)
66 # define GEN7_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM     (1 << 8)
67 
68 #define BRW_ANISORATIO_2     0
69 #define BRW_ANISORATIO_4     1
70 #define BRW_ANISORATIO_6     2
71 #define BRW_ANISORATIO_8     3
72 #define BRW_ANISORATIO_10    4
73 #define BRW_ANISORATIO_12    5
74 #define BRW_ANISORATIO_14    6
75 #define BRW_ANISORATIO_16    7
76 
77 #define BRW_BLENDFACTOR_ONE                 0x1
78 #define BRW_BLENDFACTOR_SRC_COLOR           0x2
79 #define BRW_BLENDFACTOR_SRC_ALPHA           0x3
80 #define BRW_BLENDFACTOR_DST_ALPHA           0x4
81 #define BRW_BLENDFACTOR_DST_COLOR           0x5
82 #define BRW_BLENDFACTOR_SRC_ALPHA_SATURATE  0x6
83 #define BRW_BLENDFACTOR_CONST_COLOR         0x7
84 #define BRW_BLENDFACTOR_CONST_ALPHA         0x8
85 #define BRW_BLENDFACTOR_SRC1_COLOR          0x9
86 #define BRW_BLENDFACTOR_SRC1_ALPHA          0x0A
87 #define BRW_BLENDFACTOR_ZERO                0x11
88 #define BRW_BLENDFACTOR_INV_SRC_COLOR       0x12
89 #define BRW_BLENDFACTOR_INV_SRC_ALPHA       0x13
90 #define BRW_BLENDFACTOR_INV_DST_ALPHA       0x14
91 #define BRW_BLENDFACTOR_INV_DST_COLOR       0x15
92 #define BRW_BLENDFACTOR_INV_CONST_COLOR     0x17
93 #define BRW_BLENDFACTOR_INV_CONST_ALPHA     0x18
94 #define BRW_BLENDFACTOR_INV_SRC1_COLOR      0x19
95 #define BRW_BLENDFACTOR_INV_SRC1_ALPHA      0x1A
96 
97 #define BRW_BLENDFUNCTION_ADD               0
98 #define BRW_BLENDFUNCTION_SUBTRACT          1
99 #define BRW_BLENDFUNCTION_REVERSE_SUBTRACT  2
100 #define BRW_BLENDFUNCTION_MIN               3
101 #define BRW_BLENDFUNCTION_MAX               4
102 
103 #define BRW_ALPHATEST_FORMAT_UNORM8         0
104 #define BRW_ALPHATEST_FORMAT_FLOAT32        1
105 
106 #define BRW_CHROMAKEY_KILL_ON_ANY_MATCH  0
107 #define BRW_CHROMAKEY_REPLACE_BLACK      1
108 
109 #define BRW_CLIP_API_OGL     0
110 #define BRW_CLIP_API_DX      1
111 
112 #define BRW_CLIP_NDCSPACE     0
113 #define BRW_CLIP_SCREENSPACE  1
114 
115 #define BRW_COMPAREFUNCTION_ALWAYS       0
116 #define BRW_COMPAREFUNCTION_NEVER        1
117 #define BRW_COMPAREFUNCTION_LESS         2
118 #define BRW_COMPAREFUNCTION_EQUAL        3
119 #define BRW_COMPAREFUNCTION_LEQUAL       4
120 #define BRW_COMPAREFUNCTION_GREATER      5
121 #define BRW_COMPAREFUNCTION_NOTEQUAL     6
122 #define BRW_COMPAREFUNCTION_GEQUAL       7
123 
124 #define BRW_COVERAGE_PIXELS_HALF     0
125 #define BRW_COVERAGE_PIXELS_1        1
126 #define BRW_COVERAGE_PIXELS_2        2
127 #define BRW_COVERAGE_PIXELS_4        3
128 
129 #define BRW_CULLMODE_BOTH        0
130 #define BRW_CULLMODE_NONE        1
131 #define BRW_CULLMODE_FRONT       2
132 #define BRW_CULLMODE_BACK        3
133 
134 #define BRW_DEFAULTCOLOR_R8G8B8A8_UNORM      0
135 #define BRW_DEFAULTCOLOR_R32G32B32A32_FLOAT  1
136 
137 #define BRW_DEPTHFORMAT_D32_FLOAT_S8X24_UINT     0
138 #define BRW_DEPTHFORMAT_D32_FLOAT                1
139 #define BRW_DEPTHFORMAT_D24_UNORM_S8_UINT        2
140 #define BRW_DEPTHFORMAT_D24_UNORM_X8_UINT        3 /* GEN5 */
141 #define BRW_DEPTHFORMAT_D16_UNORM                5
142 
143 #define BRW_FLOATING_POINT_IEEE_754        0
144 #define BRW_FLOATING_POINT_NON_IEEE_754    1
145 
146 #define BRW_FRONTWINDING_CW      0
147 #define BRW_FRONTWINDING_CCW     1
148 
149 #define BRW_CUT_INDEX_ENABLE     (1 << 10)
150 
151 #define BRW_INDEX_BYTE     0
152 #define BRW_INDEX_WORD     1
153 #define BRW_INDEX_DWORD    2
154 
155 #define BRW_LOGICOPFUNCTION_CLEAR            0
156 #define BRW_LOGICOPFUNCTION_NOR              1
157 #define BRW_LOGICOPFUNCTION_AND_INVERTED     2
158 #define BRW_LOGICOPFUNCTION_COPY_INVERTED    3
159 #define BRW_LOGICOPFUNCTION_AND_REVERSE      4
160 #define BRW_LOGICOPFUNCTION_INVERT           5
161 #define BRW_LOGICOPFUNCTION_XOR              6
162 #define BRW_LOGICOPFUNCTION_NAND             7
163 #define BRW_LOGICOPFUNCTION_AND              8
164 #define BRW_LOGICOPFUNCTION_EQUIV            9
165 #define BRW_LOGICOPFUNCTION_NOOP             10
166 #define BRW_LOGICOPFUNCTION_OR_INVERTED      11
167 #define BRW_LOGICOPFUNCTION_COPY             12
168 #define BRW_LOGICOPFUNCTION_OR_REVERSE       13
169 #define BRW_LOGICOPFUNCTION_OR               14
170 #define BRW_LOGICOPFUNCTION_SET              15
171 
172 #define BRW_MAPFILTER_NEAREST        0x0
173 #define BRW_MAPFILTER_LINEAR         0x1
174 #define BRW_MAPFILTER_ANISOTROPIC    0x2
175 
176 #define BRW_MIPFILTER_NONE        0
177 #define BRW_MIPFILTER_NEAREST     1
178 #define BRW_MIPFILTER_LINEAR      3
179 
180 #define BRW_ADDRESS_ROUNDING_ENABLE_U_MAG	0x20
181 #define BRW_ADDRESS_ROUNDING_ENABLE_U_MIN	0x10
182 #define BRW_ADDRESS_ROUNDING_ENABLE_V_MAG	0x08
183 #define BRW_ADDRESS_ROUNDING_ENABLE_V_MIN	0x04
184 #define BRW_ADDRESS_ROUNDING_ENABLE_R_MAG	0x02
185 #define BRW_ADDRESS_ROUNDING_ENABLE_R_MIN	0x01
186 
187 #define BRW_PREFILTER_ALWAYS     0x0
188 #define BRW_PREFILTER_NEVER      0x1
189 #define BRW_PREFILTER_LESS       0x2
190 #define BRW_PREFILTER_EQUAL      0x3
191 #define BRW_PREFILTER_LEQUAL     0x4
192 #define BRW_PREFILTER_GREATER    0x5
193 #define BRW_PREFILTER_NOTEQUAL   0x6
194 #define BRW_PREFILTER_GEQUAL     0x7
195 
196 #define BRW_PROVOKING_VERTEX_0    0
197 #define BRW_PROVOKING_VERTEX_1    1
198 #define BRW_PROVOKING_VERTEX_2    2
199 
200 #define BRW_RASTRULE_UPPER_LEFT  0
201 #define BRW_RASTRULE_UPPER_RIGHT 1
202 /* These are listed as "Reserved, but not seen as useful"
203  * in Intel documentation (page 212, "Point Rasterization Rule",
204  * section 7.4 "SF Pipeline State Summary", of document
205  * "Intel® 965 Express Chipset Family and Intel® G35 Express
206  * Chipset Graphics Controller Programmer's Reference Manual,
207  * Volume 2: 3D/Media", Revision 1.0b as of January 2008,
208  * available at
209  *     https://01.org/linuxgraphics/documentation/hardware-specification-prms
210  * at the time of this writing).
211  *
212  * These appear to be supported on at least some
213  * i965-family devices, and the BRW_RASTRULE_LOWER_RIGHT
214  * is useful when using OpenGL to render to a FBO
215  * (which has the pixel coordinate Y orientation inverted
216  * with respect to the normal OpenGL pixel coordinate system).
217  */
218 #define BRW_RASTRULE_LOWER_LEFT  2
219 #define BRW_RASTRULE_LOWER_RIGHT 3
220 
221 #define BRW_RENDERTARGET_CLAMPRANGE_UNORM    0
222 #define BRW_RENDERTARGET_CLAMPRANGE_SNORM    1
223 #define BRW_RENDERTARGET_CLAMPRANGE_FORMAT   2
224 
225 #define BRW_STENCILOP_KEEP               0
226 #define BRW_STENCILOP_ZERO               1
227 #define BRW_STENCILOP_REPLACE            2
228 #define BRW_STENCILOP_INCRSAT            3
229 #define BRW_STENCILOP_DECRSAT            4
230 #define BRW_STENCILOP_INCR               5
231 #define BRW_STENCILOP_DECR               6
232 #define BRW_STENCILOP_INVERT             7
233 
234 /* Surface state DW0 */
235 #define GEN8_SURFACE_IS_ARRAY                       (1 << 28)
236 #define GEN8_SURFACE_VALIGN_4                       (1 << 16)
237 #define GEN8_SURFACE_VALIGN_8                       (2 << 16)
238 #define GEN8_SURFACE_VALIGN_16                      (3 << 16)
239 #define GEN8_SURFACE_HALIGN_4                       (1 << 14)
240 #define GEN8_SURFACE_HALIGN_8                       (2 << 14)
241 #define GEN8_SURFACE_HALIGN_16                      (3 << 14)
242 #define GEN8_SURFACE_TILING_NONE                    (0 << 12)
243 #define GEN8_SURFACE_TILING_W                       (1 << 12)
244 #define GEN8_SURFACE_TILING_X                       (2 << 12)
245 #define GEN8_SURFACE_TILING_Y                       (3 << 12)
246 #define GEN8_SURFACE_SAMPLER_L2_BYPASS_DISABLE      (1 << 9)
247 #define BRW_SURFACE_RC_READ_WRITE	(1 << 8)
248 #define BRW_SURFACE_MIPLAYOUT_SHIFT	10
249 #define BRW_SURFACE_MIPMAPLAYOUT_BELOW   0
250 #define BRW_SURFACE_MIPMAPLAYOUT_RIGHT   1
251 #define BRW_SURFACE_CUBEFACE_ENABLES	0x3f
252 #define BRW_SURFACE_BLEND_ENABLED	(1 << 13)
253 #define BRW_SURFACE_WRITEDISABLE_B_SHIFT	14
254 #define BRW_SURFACE_WRITEDISABLE_G_SHIFT	15
255 #define BRW_SURFACE_WRITEDISABLE_R_SHIFT	16
256 #define BRW_SURFACE_WRITEDISABLE_A_SHIFT	17
257 
258 #define GEN9_SURFACE_ASTC_HDR_FORMAT_BIT                 0x100
259 
260 #define BRW_SURFACE_FORMAT_SHIFT	18
261 #define BRW_SURFACE_FORMAT_MASK		INTEL_MASK(26, 18)
262 
263 #define BRW_SURFACERETURNFORMAT_FLOAT32  0
264 #define BRW_SURFACERETURNFORMAT_S1       1
265 
266 #define BRW_SURFACE_TYPE_SHIFT		29
267 #define BRW_SURFACE_TYPE_MASK		INTEL_MASK(31, 29)
268 #define BRW_SURFACE_1D      0
269 #define BRW_SURFACE_2D      1
270 #define BRW_SURFACE_3D      2
271 #define BRW_SURFACE_CUBE    3
272 #define BRW_SURFACE_BUFFER  4
273 #define BRW_SURFACE_NULL    7
274 
275 #define GEN7_SURFACE_IS_ARRAY           (1 << 28)
276 #define GEN7_SURFACE_VALIGN_2           (0 << 16)
277 #define GEN7_SURFACE_VALIGN_4           (1 << 16)
278 #define GEN7_SURFACE_HALIGN_4           (0 << 15)
279 #define GEN7_SURFACE_HALIGN_8           (1 << 15)
280 #define GEN7_SURFACE_TILING_NONE        (0 << 13)
281 #define GEN7_SURFACE_TILING_X           (2 << 13)
282 #define GEN7_SURFACE_TILING_Y           (3 << 13)
283 #define GEN7_SURFACE_ARYSPC_FULL	(0 << 10)
284 #define GEN7_SURFACE_ARYSPC_LOD0	(1 << 10)
285 
286 /* Surface state DW1 */
287 #define GEN8_SURFACE_MOCS_SHIFT         24
288 #define GEN8_SURFACE_MOCS_MASK          INTEL_MASK(30, 24)
289 #define GEN8_SURFACE_QPITCH_SHIFT       0
290 #define GEN8_SURFACE_QPITCH_MASK        INTEL_MASK(14, 0)
291 
292 /* Surface state DW2 */
293 #define BRW_SURFACE_HEIGHT_SHIFT	19
294 #define BRW_SURFACE_HEIGHT_MASK		INTEL_MASK(31, 19)
295 #define BRW_SURFACE_WIDTH_SHIFT		6
296 #define BRW_SURFACE_WIDTH_MASK		INTEL_MASK(18, 6)
297 #define BRW_SURFACE_LOD_SHIFT		2
298 #define BRW_SURFACE_LOD_MASK		INTEL_MASK(5, 2)
299 #define GEN7_SURFACE_HEIGHT_SHIFT       16
300 #define GEN7_SURFACE_HEIGHT_MASK        INTEL_MASK(29, 16)
301 #define GEN7_SURFACE_WIDTH_SHIFT        0
302 #define GEN7_SURFACE_WIDTH_MASK         INTEL_MASK(13, 0)
303 
304 /* Surface state DW3 */
305 #define BRW_SURFACE_DEPTH_SHIFT		21
306 #define BRW_SURFACE_DEPTH_MASK		INTEL_MASK(31, 21)
307 #define BRW_SURFACE_PITCH_SHIFT		3
308 #define BRW_SURFACE_PITCH_MASK		INTEL_MASK(19, 3)
309 #define BRW_SURFACE_TILED		(1 << 1)
310 #define BRW_SURFACE_TILED_Y		(1 << 0)
311 #define HSW_SURFACE_IS_INTEGER_FORMAT   (1 << 18)
312 
313 /* Surface state DW4 */
314 #define BRW_SURFACE_MIN_LOD_SHIFT	28
315 #define BRW_SURFACE_MIN_LOD_MASK	INTEL_MASK(31, 28)
316 #define BRW_SURFACE_MIN_ARRAY_ELEMENT_SHIFT	17
317 #define BRW_SURFACE_MIN_ARRAY_ELEMENT_MASK	INTEL_MASK(27, 17)
318 #define BRW_SURFACE_RENDER_TARGET_VIEW_EXTENT_SHIFT	8
319 #define BRW_SURFACE_RENDER_TARGET_VIEW_EXTENT_MASK	INTEL_MASK(16, 8)
320 #define BRW_SURFACE_MULTISAMPLECOUNT_1  (0 << 4)
321 #define BRW_SURFACE_MULTISAMPLECOUNT_4  (2 << 4)
322 #define GEN7_SURFACE_MULTISAMPLECOUNT_1         (0 << 3)
323 #define GEN8_SURFACE_MULTISAMPLECOUNT_2         (1 << 3)
324 #define GEN7_SURFACE_MULTISAMPLECOUNT_4         (2 << 3)
325 #define GEN7_SURFACE_MULTISAMPLECOUNT_8         (3 << 3)
326 #define GEN8_SURFACE_MULTISAMPLECOUNT_16        (4 << 3)
327 #define GEN7_SURFACE_MSFMT_MSS                  (0 << 6)
328 #define GEN7_SURFACE_MSFMT_DEPTH_STENCIL        (1 << 6)
329 #define GEN7_SURFACE_MIN_ARRAY_ELEMENT_SHIFT	18
330 #define GEN7_SURFACE_MIN_ARRAY_ELEMENT_MASK     INTEL_MASK(28, 18)
331 #define GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_SHIFT	7
332 #define GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_MASK   INTEL_MASK(17, 7)
333 
334 /* Surface state DW5 */
335 #define BRW_SURFACE_X_OFFSET_SHIFT		25
336 #define BRW_SURFACE_X_OFFSET_MASK		INTEL_MASK(31, 25)
337 #define BRW_SURFACE_VERTICAL_ALIGN_ENABLE	(1 << 24)
338 #define BRW_SURFACE_Y_OFFSET_SHIFT		20
339 #define BRW_SURFACE_Y_OFFSET_MASK		INTEL_MASK(23, 20)
340 #define GEN7_SURFACE_MIN_LOD_SHIFT              4
341 #define GEN7_SURFACE_MIN_LOD_MASK               INTEL_MASK(7, 4)
342 #define GEN8_SURFACE_Y_OFFSET_SHIFT		21
343 #define GEN8_SURFACE_Y_OFFSET_MASK		INTEL_MASK(23, 21)
344 
345 #define GEN7_SURFACE_MOCS_SHIFT                 16
346 #define GEN7_SURFACE_MOCS_MASK                  INTEL_MASK(19, 16)
347 
348 #define GEN9_SURFACE_MIP_TAIL_START_LOD_SHIFT      8
349 #define GEN9_SURFACE_MIP_TAIL_START_LOD_MASK       INTEL_MASK(11, 8)
350 
351 /* Surface state DW6 */
352 #define GEN7_SURFACE_MCS_ENABLE                 (1 << 0)
353 #define GEN7_SURFACE_MCS_PITCH_SHIFT            3
354 #define GEN7_SURFACE_MCS_PITCH_MASK             INTEL_MASK(11, 3)
355 #define GEN8_SURFACE_AUX_QPITCH_SHIFT           16
356 #define GEN8_SURFACE_AUX_QPITCH_MASK            INTEL_MASK(30, 16)
357 #define GEN8_SURFACE_AUX_PITCH_SHIFT            3
358 #define GEN8_SURFACE_AUX_PITCH_MASK             INTEL_MASK(11, 3)
359 #define GEN8_SURFACE_AUX_MODE_MASK              INTEL_MASK(2, 0)
360 
361 #define GEN8_SURFACE_AUX_MODE_NONE              0
362 #define GEN8_SURFACE_AUX_MODE_MCS               1
363 #define GEN8_SURFACE_AUX_MODE_APPEND            2
364 #define GEN8_SURFACE_AUX_MODE_HIZ               3
365 #define GEN9_SURFACE_AUX_MODE_CCS_E             5
366 
367 /* Surface state DW7 */
368 #define GEN9_SURFACE_RT_COMPRESSION_SHIFT       30
369 #define GEN9_SURFACE_RT_COMPRESSION_MASK        INTEL_MASK(30, 30)
370 #define GEN7_SURFACE_CLEAR_COLOR_SHIFT		28
371 #define GEN7_SURFACE_SCS_R_SHIFT                25
372 #define GEN7_SURFACE_SCS_R_MASK                 INTEL_MASK(27, 25)
373 #define GEN7_SURFACE_SCS_G_SHIFT                22
374 #define GEN7_SURFACE_SCS_G_MASK                 INTEL_MASK(24, 22)
375 #define GEN7_SURFACE_SCS_B_SHIFT                19
376 #define GEN7_SURFACE_SCS_B_MASK                 INTEL_MASK(21, 19)
377 #define GEN7_SURFACE_SCS_A_SHIFT                16
378 #define GEN7_SURFACE_SCS_A_MASK                 INTEL_MASK(18, 16)
379 
380 /* The actual swizzle values/what channel to use */
381 #define HSW_SCS_ZERO                     0
382 #define HSW_SCS_ONE                      1
383 #define HSW_SCS_RED                      4
384 #define HSW_SCS_GREEN                    5
385 #define HSW_SCS_BLUE                     6
386 #define HSW_SCS_ALPHA                    7
387 
388 /* SAMPLER_STATE DW0 */
389 #define BRW_SAMPLER_DISABLE                     (1 << 31)
390 #define BRW_SAMPLER_LOD_PRECLAMP_ENABLE         (1 << 28)
391 #define GEN6_SAMPLER_MIN_MAG_NOT_EQUAL          (1 << 27) /* Gen6 only */
392 #define BRW_SAMPLER_BASE_MIPLEVEL_MASK          INTEL_MASK(26, 22)
393 #define BRW_SAMPLER_BASE_MIPLEVEL_SHIFT         22
394 #define BRW_SAMPLER_MIP_FILTER_MASK             INTEL_MASK(21, 20)
395 #define BRW_SAMPLER_MIP_FILTER_SHIFT            20
396 #define BRW_SAMPLER_MAG_FILTER_MASK             INTEL_MASK(19, 17)
397 #define BRW_SAMPLER_MAG_FILTER_SHIFT            17
398 #define BRW_SAMPLER_MIN_FILTER_MASK             INTEL_MASK(16, 14)
399 #define BRW_SAMPLER_MIN_FILTER_SHIFT            14
400 #define GEN4_SAMPLER_LOD_BIAS_MASK              INTEL_MASK(13, 3)
401 #define GEN4_SAMPLER_LOD_BIAS_SHIFT             3
402 #define GEN4_SAMPLER_SHADOW_FUNCTION_MASK       INTEL_MASK(2, 0)
403 #define GEN4_SAMPLER_SHADOW_FUNCTION_SHIFT      0
404 
405 #define GEN7_SAMPLER_LOD_BIAS_MASK              INTEL_MASK(13, 1)
406 #define GEN7_SAMPLER_LOD_BIAS_SHIFT             1
407 #define GEN7_SAMPLER_EWA_ANISOTROPIC_ALGORITHM  (1 << 0)
408 
409 /* SAMPLER_STATE DW1 */
410 #define GEN4_SAMPLER_MIN_LOD_MASK               INTEL_MASK(31, 22)
411 #define GEN4_SAMPLER_MIN_LOD_SHIFT              22
412 #define GEN4_SAMPLER_MAX_LOD_MASK               INTEL_MASK(21, 12)
413 #define GEN4_SAMPLER_MAX_LOD_SHIFT              12
414 #define GEN4_SAMPLER_CUBE_CONTROL_OVERRIDE      (1 << 9)
415 /* Wrap modes are in DW1 on Gen4-6 and DW3 on Gen7+ */
416 #define BRW_SAMPLER_TCX_WRAP_MODE_MASK          INTEL_MASK(8, 6)
417 #define BRW_SAMPLER_TCX_WRAP_MODE_SHIFT         6
418 #define BRW_SAMPLER_TCY_WRAP_MODE_MASK          INTEL_MASK(5, 3)
419 #define BRW_SAMPLER_TCY_WRAP_MODE_SHIFT         3
420 #define BRW_SAMPLER_TCZ_WRAP_MODE_MASK          INTEL_MASK(2, 0)
421 #define BRW_SAMPLER_TCZ_WRAP_MODE_SHIFT         0
422 
423 #define GEN7_SAMPLER_MIN_LOD_MASK               INTEL_MASK(31, 20)
424 #define GEN7_SAMPLER_MIN_LOD_SHIFT              20
425 #define GEN7_SAMPLER_MAX_LOD_MASK               INTEL_MASK(19, 8)
426 #define GEN7_SAMPLER_MAX_LOD_SHIFT              8
427 #define GEN7_SAMPLER_SHADOW_FUNCTION_MASK       INTEL_MASK(3, 1)
428 #define GEN7_SAMPLER_SHADOW_FUNCTION_SHIFT      1
429 #define GEN7_SAMPLER_CUBE_CONTROL_OVERRIDE      (1 << 0)
430 
431 /* SAMPLER_STATE DW2 - border color pointer */
432 
433 /* SAMPLER_STATE DW3 */
434 #define BRW_SAMPLER_MAX_ANISOTROPY_MASK         INTEL_MASK(21, 19)
435 #define BRW_SAMPLER_MAX_ANISOTROPY_SHIFT        19
436 #define BRW_SAMPLER_ADDRESS_ROUNDING_MASK       INTEL_MASK(18, 13)
437 #define BRW_SAMPLER_ADDRESS_ROUNDING_SHIFT      13
438 #define GEN7_SAMPLER_NON_NORMALIZED_COORDINATES (1 << 10)
439 /* Gen7+ wrap modes reuse the same BRW_SAMPLER_TC*_WRAP_MODE enums. */
440 #define GEN6_SAMPLER_NON_NORMALIZED_COORDINATES (1 << 0)
441 
442 enum brw_wrap_mode {
443    BRW_TEXCOORDMODE_WRAP         = 0,
444    BRW_TEXCOORDMODE_MIRROR       = 1,
445    BRW_TEXCOORDMODE_CLAMP        = 2,
446    BRW_TEXCOORDMODE_CUBE         = 3,
447    BRW_TEXCOORDMODE_CLAMP_BORDER = 4,
448    BRW_TEXCOORDMODE_MIRROR_ONCE  = 5,
449    GEN8_TEXCOORDMODE_HALF_BORDER = 6,
450 };
451 
452 #define BRW_THREAD_PRIORITY_NORMAL   0
453 #define BRW_THREAD_PRIORITY_HIGH     1
454 
455 #define BRW_TILEWALK_XMAJOR                 0
456 #define BRW_TILEWALK_YMAJOR                 1
457 
458 #define BRW_VERTEX_SUBPIXEL_PRECISION_8BITS  0
459 #define BRW_VERTEX_SUBPIXEL_PRECISION_4BITS  1
460 
461 
462 #define CMD_URB_FENCE                 0x6000
463 #define CMD_CS_URB_STATE              0x6001
464 #define CMD_CONST_BUFFER              0x6002
465 
466 #define CMD_STATE_BASE_ADDRESS        0x6101
467 #define CMD_STATE_SIP                 0x6102
468 #define CMD_PIPELINE_SELECT_965       0x6104
469 #define CMD_PIPELINE_SELECT_GM45      0x6904
470 
471 #define _3DSTATE_PIPELINED_POINTERS		0x7800
472 #define _3DSTATE_BINDING_TABLE_POINTERS		0x7801
473 # define GEN6_BINDING_TABLE_MODIFY_VS	(1 << 8)
474 # define GEN6_BINDING_TABLE_MODIFY_GS	(1 << 9)
475 # define GEN6_BINDING_TABLE_MODIFY_PS	(1 << 12)
476 
477 #define _3DSTATE_BINDING_TABLE_POINTERS_VS	0x7826 /* GEN7+ */
478 #define _3DSTATE_BINDING_TABLE_POINTERS_HS	0x7827 /* GEN7+ */
479 #define _3DSTATE_BINDING_TABLE_POINTERS_DS	0x7828 /* GEN7+ */
480 #define _3DSTATE_BINDING_TABLE_POINTERS_GS	0x7829 /* GEN7+ */
481 #define _3DSTATE_BINDING_TABLE_POINTERS_PS	0x782A /* GEN7+ */
482 
483 #define _3DSTATE_SAMPLER_STATE_POINTERS		0x7802 /* GEN6+ */
484 # define PS_SAMPLER_STATE_CHANGE				(1 << 12)
485 # define GS_SAMPLER_STATE_CHANGE				(1 << 9)
486 # define VS_SAMPLER_STATE_CHANGE				(1 << 8)
487 /* DW1: VS */
488 /* DW2: GS */
489 /* DW3: PS */
490 
491 #define _3DSTATE_SAMPLER_STATE_POINTERS_VS	0x782B /* GEN7+ */
492 #define _3DSTATE_SAMPLER_STATE_POINTERS_HS	0x782C /* GEN7+ */
493 #define _3DSTATE_SAMPLER_STATE_POINTERS_DS	0x782D /* GEN7+ */
494 #define _3DSTATE_SAMPLER_STATE_POINTERS_GS	0x782E /* GEN7+ */
495 #define _3DSTATE_SAMPLER_STATE_POINTERS_PS	0x782F /* GEN7+ */
496 
497 #define _3DSTATE_VERTEX_BUFFERS       0x7808
498 # define BRW_VB0_INDEX_SHIFT		27
499 # define GEN6_VB0_INDEX_SHIFT		26
500 # define BRW_VB0_ACCESS_VERTEXDATA	(0 << 26)
501 # define BRW_VB0_ACCESS_INSTANCEDATA	(1 << 26)
502 # define GEN6_VB0_ACCESS_VERTEXDATA	(0 << 20)
503 # define GEN6_VB0_ACCESS_INSTANCEDATA	(1 << 20)
504 # define GEN7_VB0_ADDRESS_MODIFYENABLE  (1 << 14)
505 # define BRW_VB0_PITCH_SHIFT		0
506 
507 #define _3DSTATE_VERTEX_ELEMENTS      0x7809
508 # define BRW_VE0_INDEX_SHIFT		27
509 # define GEN6_VE0_INDEX_SHIFT		26
510 # define BRW_VE0_FORMAT_SHIFT		16
511 # define BRW_VE0_VALID			(1 << 26)
512 # define GEN6_VE0_VALID			(1 << 25)
513 # define GEN6_VE0_EDGE_FLAG_ENABLE	(1 << 15)
514 # define BRW_VE0_SRC_OFFSET_SHIFT	0
515 # define BRW_VE1_COMPONENT_NOSTORE	0
516 # define BRW_VE1_COMPONENT_STORE_SRC	1
517 # define BRW_VE1_COMPONENT_STORE_0	2
518 # define BRW_VE1_COMPONENT_STORE_1_FLT	3
519 # define BRW_VE1_COMPONENT_STORE_1_INT	4
520 # define BRW_VE1_COMPONENT_STORE_VID	5
521 # define BRW_VE1_COMPONENT_STORE_IID	6
522 # define BRW_VE1_COMPONENT_STORE_PID	7
523 # define BRW_VE1_COMPONENT_0_SHIFT	28
524 # define BRW_VE1_COMPONENT_1_SHIFT	24
525 # define BRW_VE1_COMPONENT_2_SHIFT	20
526 # define BRW_VE1_COMPONENT_3_SHIFT	16
527 # define BRW_VE1_DST_OFFSET_SHIFT	0
528 
529 #define CMD_INDEX_BUFFER              0x780a
530 #define GEN4_3DSTATE_VF_STATISTICS		0x780b
531 #define GM45_3DSTATE_VF_STATISTICS		0x680b
532 #define _3DSTATE_CC_STATE_POINTERS		0x780e /* GEN6+ */
533 #define _3DSTATE_BLEND_STATE_POINTERS		0x7824 /* GEN7+ */
534 #define _3DSTATE_DEPTH_STENCIL_STATE_POINTERS	0x7825 /* GEN7+ */
535 
536 #define _3DSTATE_URB				0x7805 /* GEN6 */
537 # define GEN6_URB_VS_SIZE_SHIFT				16
538 # define GEN6_URB_VS_ENTRIES_SHIFT			0
539 # define GEN6_URB_GS_ENTRIES_SHIFT			8
540 # define GEN6_URB_GS_SIZE_SHIFT				0
541 
542 #define _3DSTATE_VF                             0x780c /* GEN7.5+ */
543 #define HSW_CUT_INDEX_ENABLE                            (1 << 8)
544 
545 #define _3DSTATE_VF_INSTANCING                  0x7849 /* GEN8+ */
546 # define GEN8_VF_INSTANCING_ENABLE                      (1 << 8)
547 
548 #define _3DSTATE_VF_SGVS                        0x784a /* GEN8+ */
549 # define GEN8_SGVS_ENABLE_INSTANCE_ID                   (1 << 31)
550 # define GEN8_SGVS_INSTANCE_ID_COMPONENT_SHIFT          29
551 # define GEN8_SGVS_INSTANCE_ID_ELEMENT_OFFSET_SHIFT     16
552 # define GEN8_SGVS_ENABLE_VERTEX_ID                     (1 << 15)
553 # define GEN8_SGVS_VERTEX_ID_COMPONENT_SHIFT            13
554 # define GEN8_SGVS_VERTEX_ID_ELEMENT_OFFSET_SHIFT       0
555 
556 #define _3DSTATE_VF_TOPOLOGY                    0x784b /* GEN8+ */
557 
558 #define _3DSTATE_WM_CHROMAKEY			0x784c /* GEN8+ */
559 
560 #define _3DSTATE_URB_VS                         0x7830 /* GEN7+ */
561 #define _3DSTATE_URB_HS                         0x7831 /* GEN7+ */
562 #define _3DSTATE_URB_DS                         0x7832 /* GEN7+ */
563 #define _3DSTATE_URB_GS                         0x7833 /* GEN7+ */
564 # define GEN7_URB_ENTRY_SIZE_SHIFT                      16
565 # define GEN7_URB_STARTING_ADDRESS_SHIFT                25
566 
567 #define _3DSTATE_PUSH_CONSTANT_ALLOC_VS         0x7912 /* GEN7+ */
568 #define _3DSTATE_PUSH_CONSTANT_ALLOC_HS         0x7913 /* GEN7+ */
569 #define _3DSTATE_PUSH_CONSTANT_ALLOC_DS         0x7914 /* GEN7+ */
570 #define _3DSTATE_PUSH_CONSTANT_ALLOC_GS         0x7915 /* GEN7+ */
571 #define _3DSTATE_PUSH_CONSTANT_ALLOC_PS         0x7916 /* GEN7+ */
572 # define GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT         16
573 
574 #define _3DSTATE_VIEWPORT_STATE_POINTERS	0x780d /* GEN6+ */
575 # define GEN6_CC_VIEWPORT_MODIFY			(1 << 12)
576 # define GEN6_SF_VIEWPORT_MODIFY			(1 << 11)
577 # define GEN6_CLIP_VIEWPORT_MODIFY			(1 << 10)
578 # define GEN6_NUM_VIEWPORTS				16
579 
580 #define _3DSTATE_VIEWPORT_STATE_POINTERS_CC	0x7823 /* GEN7+ */
581 #define _3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL	0x7821 /* GEN7+ */
582 
583 #define _3DSTATE_SCISSOR_STATE_POINTERS		0x780f /* GEN6+ */
584 
585 #define _3DSTATE_VS				0x7810 /* GEN6+ */
586 /* DW2 */
587 # define GEN6_VS_SPF_MODE				(1 << 31)
588 # define GEN6_VS_VECTOR_MASK_ENABLE			(1 << 30)
589 # define GEN6_VS_SAMPLER_COUNT_SHIFT			27
590 # define GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT	18
591 # define GEN6_VS_FLOATING_POINT_MODE_IEEE_754		(0 << 16)
592 # define GEN6_VS_FLOATING_POINT_MODE_ALT		(1 << 16)
593 # define HSW_VS_UAV_ACCESS_ENABLE                       (1 << 12)
594 /* DW4 */
595 # define GEN6_VS_DISPATCH_START_GRF_SHIFT		20
596 # define GEN6_VS_URB_READ_LENGTH_SHIFT			11
597 # define GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT		4
598 /* DW5 */
599 # define GEN6_VS_MAX_THREADS_SHIFT			25
600 # define HSW_VS_MAX_THREADS_SHIFT			23
601 # define GEN6_VS_STATISTICS_ENABLE			(1 << 10)
602 # define GEN6_VS_CACHE_DISABLE				(1 << 1)
603 # define GEN6_VS_ENABLE					(1 << 0)
604 /* Gen8+ DW7 */
605 # define GEN8_VS_SIMD8_ENABLE                           (1 << 2)
606 /* Gen8+ DW8 */
607 # define GEN8_VS_URB_ENTRY_OUTPUT_OFFSET_SHIFT          21
608 # define GEN8_VS_URB_OUTPUT_LENGTH_SHIFT                16
609 # define GEN8_VS_USER_CLIP_DISTANCE_SHIFT               8
610 
611 #define _3DSTATE_GS		      		0x7811 /* GEN6+ */
612 /* DW2 */
613 # define GEN6_GS_SPF_MODE				(1 << 31)
614 # define GEN6_GS_VECTOR_MASK_ENABLE			(1 << 30)
615 # define GEN6_GS_SAMPLER_COUNT_SHIFT			27
616 # define GEN6_GS_BINDING_TABLE_ENTRY_COUNT_SHIFT	18
617 # define GEN6_GS_FLOATING_POINT_MODE_IEEE_754		(0 << 16)
618 # define GEN6_GS_FLOATING_POINT_MODE_ALT		(1 << 16)
619 # define HSW_GS_UAV_ACCESS_ENABLE       		(1 << 12)
620 /* DW4 */
621 # define GEN7_GS_OUTPUT_VERTEX_SIZE_SHIFT		23
622 # define GEN7_GS_OUTPUT_TOPOLOGY_SHIFT			17
623 # define GEN6_GS_URB_READ_LENGTH_SHIFT			11
624 # define GEN7_GS_INCLUDE_VERTEX_HANDLES		        (1 << 10)
625 # define GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT		4
626 # define GEN6_GS_DISPATCH_START_GRF_SHIFT		0
627 /* DW5 */
628 # define GEN6_GS_MAX_THREADS_SHIFT			25
629 # define HSW_GS_MAX_THREADS_SHIFT			24
630 # define IVB_GS_CONTROL_DATA_FORMAT_SHIFT		24
631 # define GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT		0
632 # define GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID		1
633 # define GEN7_GS_CONTROL_DATA_HEADER_SIZE_SHIFT		20
634 # define GEN7_GS_INSTANCE_CONTROL_SHIFT			15
635 # define GEN7_GS_DISPATCH_MODE_SHIFT                    11
636 # define GEN7_GS_DISPATCH_MODE_MASK                     INTEL_MASK(12, 11)
637 # define GEN6_GS_STATISTICS_ENABLE			(1 << 10)
638 # define GEN6_GS_SO_STATISTICS_ENABLE			(1 << 9)
639 # define GEN6_GS_RENDERING_ENABLE			(1 << 8)
640 # define GEN7_GS_INCLUDE_PRIMITIVE_ID			(1 << 4)
641 # define GEN7_GS_REORDER_TRAILING			(1 << 2)
642 # define GEN7_GS_ENABLE					(1 << 0)
643 /* DW6 */
644 # define HSW_GS_CONTROL_DATA_FORMAT_SHIFT		31
645 # define GEN6_GS_REORDER				(1 << 30)
646 # define GEN6_GS_DISCARD_ADJACENCY			(1 << 29)
647 # define GEN6_GS_SVBI_PAYLOAD_ENABLE			(1 << 28)
648 # define GEN6_GS_SVBI_POSTINCREMENT_ENABLE		(1 << 27)
649 # define GEN6_GS_SVBI_POSTINCREMENT_VALUE_SHIFT		16
650 # define GEN6_GS_SVBI_POSTINCREMENT_VALUE_MASK		INTEL_MASK(25, 16)
651 # define GEN6_GS_ENABLE					(1 << 15)
652 
653 /* Gen8+ DW8 */
654 # define GEN8_GS_STATIC_OUTPUT                          (1 << 30)
655 # define GEN8_GS_STATIC_VERTEX_COUNT_SHIFT              16
656 # define GEN8_GS_STATIC_VERTEX_COUNT_MASK               INTEL_MASK(26, 16)
657 
658 /* Gen8+ DW9 */
659 # define GEN8_GS_URB_ENTRY_OUTPUT_OFFSET_SHIFT          21
660 # define GEN8_GS_URB_OUTPUT_LENGTH_SHIFT                16
661 # define GEN8_GS_USER_CLIP_DISTANCE_SHIFT               8
662 
663 # define BRW_GS_EDGE_INDICATOR_0			(1 << 8)
664 # define BRW_GS_EDGE_INDICATOR_1			(1 << 9)
665 
666 #define _3DSTATE_HS                             0x781B /* GEN7+ */
667 /* DW1 */
668 # define GEN7_HS_SAMPLER_COUNT_MASK                     INTEL_MASK(29, 27)
669 # define GEN7_HS_SAMPLER_COUNT_SHIFT                    27
670 # define GEN7_HS_BINDING_TABLE_ENTRY_COUNT_MASK         INTEL_MASK(25, 18)
671 # define GEN7_HS_BINDING_TABLE_ENTRY_COUNT_SHIFT        18
672 # define GEN7_HS_FLOATING_POINT_MODE_IEEE_754           (0 << 16)
673 # define GEN7_HS_FLOATING_POINT_MODE_ALT                (1 << 16)
674 # define GEN7_HS_MAX_THREADS_SHIFT                      0
675 /* DW2 */
676 # define GEN7_HS_ENABLE                                 (1 << 31)
677 # define GEN7_HS_STATISTICS_ENABLE                      (1 << 29)
678 # define GEN8_HS_MAX_THREADS_SHIFT                      8
679 # define GEN7_HS_INSTANCE_COUNT_MASK                    INTEL_MASK(3, 0)
680 # define GEN7_HS_INSTANCE_COUNT_SHIFT                   0
681 /* DW5 */
682 # define GEN7_HS_SINGLE_PROGRAM_FLOW                    (1 << 27)
683 # define GEN7_HS_VECTOR_MASK_ENABLE                     (1 << 26)
684 # define HSW_HS_ACCESSES_UAV                            (1 << 25)
685 # define GEN7_HS_INCLUDE_VERTEX_HANDLES                 (1 << 24)
686 # define GEN7_HS_DISPATCH_START_GRF_MASK                INTEL_MASK(23, 19)
687 # define GEN7_HS_DISPATCH_START_GRF_SHIFT               19
688 # define GEN7_HS_URB_READ_LENGTH_MASK                   INTEL_MASK(16, 11)
689 # define GEN7_HS_URB_READ_LENGTH_SHIFT                  11
690 # define GEN7_HS_URB_ENTRY_READ_OFFSET_MASK             INTEL_MASK(9, 4)
691 # define GEN7_HS_URB_ENTRY_READ_OFFSET_SHIFT            4
692 
693 #define _3DSTATE_TE                             0x781C /* GEN7+ */
694 /* DW1 */
695 # define GEN7_TE_PARTITIONING_SHIFT                     12
696 # define GEN7_TE_OUTPUT_TOPOLOGY_SHIFT                  8
697 # define GEN7_TE_DOMAIN_SHIFT                           4
698 //# define GEN7_TE_MODE_SW                                (1 << 1)
699 # define GEN7_TE_ENABLE                                 (1 << 0)
700 
701 #define _3DSTATE_DS                             0x781D /* GEN7+ */
702 /* DW2 */
703 # define GEN7_DS_SINGLE_DOMAIN_POINT_DISPATCH           (1 << 31)
704 # define GEN7_DS_VECTOR_MASK_ENABLE                     (1 << 30)
705 # define GEN7_DS_SAMPLER_COUNT_MASK                     INTEL_MASK(29, 27)
706 # define GEN7_DS_SAMPLER_COUNT_SHIFT                    27
707 # define GEN7_DS_BINDING_TABLE_ENTRY_COUNT_MASK         INTEL_MASK(25, 18)
708 # define GEN7_DS_BINDING_TABLE_ENTRY_COUNT_SHIFT        18
709 # define GEN7_DS_FLOATING_POINT_MODE_IEEE_754           (0 << 16)
710 # define GEN7_DS_FLOATING_POINT_MODE_ALT                (1 << 16)
711 # define HSW_DS_ACCESSES_UAV                            (1 << 14)
712 /* DW4 */
713 # define GEN7_DS_DISPATCH_START_GRF_MASK                INTEL_MASK(24, 20)
714 # define GEN7_DS_DISPATCH_START_GRF_SHIFT               20
715 # define GEN7_DS_URB_READ_LENGTH_MASK                   INTEL_MASK(17, 11)
716 # define GEN7_DS_URB_READ_LENGTH_SHIFT                  11
717 # define GEN7_DS_URB_ENTRY_READ_OFFSET_MASK             INTEL_MASK(9, 4)
718 # define GEN7_DS_URB_ENTRY_READ_OFFSET_SHIFT            4
719 /* DW5 */
720 # define GEN7_DS_MAX_THREADS_SHIFT                      25
721 # define HSW_DS_MAX_THREADS_SHIFT                       21
722 # define GEN7_DS_STATISTICS_ENABLE                      (1 << 10)
723 # define GEN7_DS_SIMD8_DISPATCH_ENABLE                  (1 << 3)
724 # define GEN7_DS_COMPUTE_W_COORDINATE_ENABLE            (1 << 2)
725 # define GEN7_DS_CACHE_DISABLE                          (1 << 1)
726 # define GEN7_DS_ENABLE                                 (1 << 0)
727 /* Gen8+ DW8 */
728 # define GEN8_DS_URB_ENTRY_OUTPUT_OFFSET_MASK           INTEL_MASK(26, 21)
729 # define GEN8_DS_URB_ENTRY_OUTPUT_OFFSET_SHIFT          21
730 # define GEN8_DS_URB_OUTPUT_LENGTH_MASK                 INTEL_MASK(20, 16)
731 # define GEN8_DS_URB_OUTPUT_LENGTH_SHIFT                16
732 # define GEN8_DS_USER_CLIP_DISTANCE_MASK                INTEL_MASK(15, 8)
733 # define GEN8_DS_USER_CLIP_DISTANCE_SHIFT               8
734 # define GEN8_DS_USER_CULL_DISTANCE_MASK                INTEL_MASK(7, 0)
735 # define GEN8_DS_USER_CULL_DISTANCE_SHIFT               0
736 
737 
738 #define _3DSTATE_CLIP				0x7812 /* GEN6+ */
739 /* DW1 */
740 # define GEN7_CLIP_WINDING_CW                           (0 << 20)
741 # define GEN7_CLIP_WINDING_CCW                          (1 << 20)
742 # define GEN7_CLIP_VERTEX_SUBPIXEL_PRECISION_8          (0 << 19)
743 # define GEN7_CLIP_VERTEX_SUBPIXEL_PRECISION_4          (1 << 19)
744 # define GEN7_CLIP_EARLY_CULL                           (1 << 18)
745 # define GEN8_CLIP_FORCE_USER_CLIP_DISTANCE_BITMASK     (1 << 17)
746 # define GEN7_CLIP_CULLMODE_BOTH                        (0 << 16)
747 # define GEN7_CLIP_CULLMODE_NONE                        (1 << 16)
748 # define GEN7_CLIP_CULLMODE_FRONT                       (2 << 16)
749 # define GEN7_CLIP_CULLMODE_BACK                        (3 << 16)
750 # define GEN6_CLIP_STATISTICS_ENABLE			(1 << 10)
751 /**
752  * Just does cheap culling based on the clip distance.  Bits must be
753  * disjoint with USER_CLIP_CLIP_DISTANCE bits.
754  */
755 # define GEN6_USER_CLIP_CULL_DISTANCES_SHIFT		0
756 /* DW2 */
757 # define GEN6_CLIP_ENABLE				(1 << 31)
758 # define GEN6_CLIP_API_OGL				(0 << 30)
759 # define GEN6_CLIP_API_D3D				(1 << 30)
760 # define GEN6_CLIP_XY_TEST				(1 << 28)
761 # define GEN6_CLIP_Z_TEST				(1 << 27)
762 # define GEN6_CLIP_GB_TEST				(1 << 26)
763 /** 8-bit field of which user clip distances to clip aganist. */
764 # define GEN6_USER_CLIP_CLIP_DISTANCES_SHIFT		16
765 # define GEN6_CLIP_MODE_NORMAL				(0 << 13)
766 # define GEN6_CLIP_MODE_REJECT_ALL			(3 << 13)
767 # define GEN6_CLIP_MODE_ACCEPT_ALL			(4 << 13)
768 # define GEN6_CLIP_PERSPECTIVE_DIVIDE_DISABLE		(1 << 9)
769 # define GEN6_CLIP_NON_PERSPECTIVE_BARYCENTRIC_ENABLE	(1 << 8)
770 # define GEN6_CLIP_TRI_PROVOKE_SHIFT			4
771 # define GEN6_CLIP_LINE_PROVOKE_SHIFT			2
772 # define GEN6_CLIP_TRIFAN_PROVOKE_SHIFT			0
773 /* DW3 */
774 # define GEN6_CLIP_MIN_POINT_WIDTH_SHIFT		17
775 # define GEN6_CLIP_MAX_POINT_WIDTH_SHIFT		6
776 # define GEN6_CLIP_FORCE_ZERO_RTAINDEX			(1 << 5)
777 # define GEN6_CLIP_MAX_VP_INDEX_MASK			INTEL_MASK(3, 0)
778 
779 #define _3DSTATE_SF				0x7813 /* GEN6+ */
780 /* DW1 (for gen6) */
781 # define GEN6_SF_NUM_OUTPUTS_SHIFT			22
782 # define GEN6_SF_SWIZZLE_ENABLE				(1 << 21)
783 # define GEN6_SF_POINT_SPRITE_UPPERLEFT			(0 << 20)
784 # define GEN6_SF_POINT_SPRITE_LOWERLEFT			(1 << 20)
785 # define GEN9_SF_LINE_WIDTH_SHIFT			12 /* U11.7 */
786 # define GEN6_SF_URB_ENTRY_READ_LENGTH_SHIFT		11
787 # define GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT		4
788 /* DW2 */
789 # define GEN6_SF_LEGACY_GLOBAL_DEPTH_BIAS		(1 << 11)
790 # define GEN6_SF_STATISTICS_ENABLE			(1 << 10)
791 # define GEN6_SF_GLOBAL_DEPTH_OFFSET_SOLID		(1 << 9)
792 # define GEN6_SF_GLOBAL_DEPTH_OFFSET_WIREFRAME		(1 << 8)
793 # define GEN6_SF_GLOBAL_DEPTH_OFFSET_POINT		(1 << 7)
794 # define GEN6_SF_FRONT_SOLID				(0 << 5)
795 # define GEN6_SF_FRONT_WIREFRAME			(1 << 5)
796 # define GEN6_SF_FRONT_POINT				(2 << 5)
797 # define GEN6_SF_BACK_SOLID				(0 << 3)
798 # define GEN6_SF_BACK_WIREFRAME				(1 << 3)
799 # define GEN6_SF_BACK_POINT				(2 << 3)
800 # define GEN6_SF_VIEWPORT_TRANSFORM_ENABLE		(1 << 1)
801 # define GEN6_SF_WINDING_CCW				(1 << 0)
802 /* DW3 */
803 # define GEN6_SF_LINE_AA_ENABLE				(1 << 31)
804 # define GEN6_SF_CULL_BOTH				(0 << 29)
805 # define GEN6_SF_CULL_NONE				(1 << 29)
806 # define GEN6_SF_CULL_FRONT				(2 << 29)
807 # define GEN6_SF_CULL_BACK				(3 << 29)
808 # define GEN6_SF_LINE_WIDTH_SHIFT			18 /* U3.7 */
809 # define GEN6_SF_LINE_END_CAP_WIDTH_0_5			(0 << 16)
810 # define GEN6_SF_LINE_END_CAP_WIDTH_1_0			(1 << 16)
811 # define GEN6_SF_LINE_END_CAP_WIDTH_2_0			(2 << 16)
812 # define GEN6_SF_LINE_END_CAP_WIDTH_4_0			(3 << 16)
813 # define GEN6_SF_SCISSOR_ENABLE				(1 << 11)
814 # define GEN6_SF_MSRAST_OFF_PIXEL			(0 << 8)
815 # define GEN6_SF_MSRAST_OFF_PATTERN			(1 << 8)
816 # define GEN6_SF_MSRAST_ON_PIXEL			(2 << 8)
817 # define GEN6_SF_MSRAST_ON_PATTERN			(3 << 8)
818 /* DW4 */
819 # define GEN6_SF_TRI_PROVOKE_SHIFT			29
820 # define GEN6_SF_LINE_PROVOKE_SHIFT			27
821 # define GEN6_SF_TRIFAN_PROVOKE_SHIFT			25
822 # define GEN6_SF_LINE_AA_MODE_MANHATTAN			(0 << 14)
823 # define GEN6_SF_LINE_AA_MODE_TRUE			(1 << 14)
824 # define GEN6_SF_VERTEX_SUBPIXEL_8BITS			(0 << 12)
825 # define GEN6_SF_VERTEX_SUBPIXEL_4BITS			(1 << 12)
826 # define GEN6_SF_USE_STATE_POINT_WIDTH			(1 << 11)
827 # define GEN6_SF_POINT_WIDTH_SHIFT			0 /* U8.3 */
828 /* DW5: depth offset constant */
829 /* DW6: depth offset scale */
830 /* DW7: depth offset clamp */
831 /* DW8 */
832 # define ATTRIBUTE_1_OVERRIDE_W				(1 << 31)
833 # define ATTRIBUTE_1_OVERRIDE_Z				(1 << 30)
834 # define ATTRIBUTE_1_OVERRIDE_Y				(1 << 29)
835 # define ATTRIBUTE_1_OVERRIDE_X				(1 << 28)
836 # define ATTRIBUTE_1_CONST_SOURCE_SHIFT			25
837 # define ATTRIBUTE_1_SWIZZLE_SHIFT			22
838 # define ATTRIBUTE_1_SOURCE_SHIFT			16
839 # define ATTRIBUTE_0_OVERRIDE_W				(1 << 15)
840 # define ATTRIBUTE_0_OVERRIDE_Z				(1 << 14)
841 # define ATTRIBUTE_0_OVERRIDE_Y				(1 << 13)
842 # define ATTRIBUTE_0_OVERRIDE_X				(1 << 12)
843 # define ATTRIBUTE_0_CONST_SOURCE_SHIFT			9
844 #  define ATTRIBUTE_CONST_0000				0
845 #  define ATTRIBUTE_CONST_0001_FLOAT			1
846 #  define ATTRIBUTE_CONST_1111_FLOAT			2
847 #  define ATTRIBUTE_CONST_PRIM_ID			3
848 # define ATTRIBUTE_0_SWIZZLE_SHIFT			6
849 # define ATTRIBUTE_0_SOURCE_SHIFT			0
850 
851 # define ATTRIBUTE_SWIZZLE_INPUTATTR                    0
852 # define ATTRIBUTE_SWIZZLE_INPUTATTR_FACING             1
853 # define ATTRIBUTE_SWIZZLE_INPUTATTR_W                  2
854 # define ATTRIBUTE_SWIZZLE_INPUTATTR_FACING_W           3
855 # define ATTRIBUTE_SWIZZLE_SHIFT                        6
856 
857 /* DW16: Point sprite texture coordinate enables */
858 /* DW17: Constant interpolation enables */
859 /* DW18: attr 0-7 wrap shortest enables */
860 /* DW19: attr 8-16 wrap shortest enables */
861 
862 /* On GEN7, many fields of 3DSTATE_SF were split out into a new command:
863  * 3DSTATE_SBE.  The remaining fields live in different DWords, but retain
864  * the same bit-offset.  The only new field:
865  */
866 /* GEN7/DW1: */
867 # define GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT	12
868 /* GEN7/DW2: */
869 # define HSW_SF_LINE_STIPPLE_ENABLE			(1 << 14)
870 
871 # define GEN8_SF_SMOOTH_POINT_ENABLE                    (1 << 13)
872 
873 #define _3DSTATE_SBE				0x781F /* GEN7+ */
874 /* DW1 */
875 # define GEN8_SBE_FORCE_URB_ENTRY_READ_LENGTH           (1 << 29)
876 # define GEN8_SBE_FORCE_URB_ENTRY_READ_OFFSET           (1 << 28)
877 # define GEN7_SBE_SWIZZLE_CONTROL_MODE			(1 << 28)
878 # define GEN7_SBE_NUM_OUTPUTS_SHIFT			22
879 # define GEN7_SBE_SWIZZLE_ENABLE			(1 << 21)
880 # define GEN7_SBE_POINT_SPRITE_LOWERLEFT		(1 << 20)
881 # define GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT		11
882 # define GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT		4
883 # define GEN8_SBE_URB_ENTRY_READ_OFFSET_SHIFT		5
884 /* DW2-9: Attribute setup (same as DW8-15 of gen6 _3DSTATE_SF) */
885 /* DW10: Point sprite texture coordinate enables */
886 /* DW11: Constant interpolation enables */
887 /* DW12: attr 0-7 wrap shortest enables */
888 /* DW13: attr 8-16 wrap shortest enables */
889 
890 /* DW4-5: Attribute active components (gen9) */
891 #define GEN9_SBE_ACTIVE_COMPONENT_NONE			0
892 #define GEN9_SBE_ACTIVE_COMPONENT_XY			1
893 #define GEN9_SBE_ACTIVE_COMPONENT_XYZ			2
894 #define GEN9_SBE_ACTIVE_COMPONENT_XYZW			3
895 
896 #define _3DSTATE_SBE_SWIZ                       0x7851 /* GEN8+ */
897 
898 #define _3DSTATE_RASTER                         0x7850 /* GEN8+ */
899 /* DW1 */
900 # define GEN9_RASTER_VIEWPORT_Z_FAR_CLIP_TEST_ENABLE    (1 << 26)
901 # define GEN9_RASTER_CONSERVATIVE_RASTERIZATION_ENABLE  (1 << 24)
902 # define GEN8_RASTER_FRONT_WINDING_CCW                  (1 << 21)
903 # define GEN8_RASTER_CULL_BOTH                          (0 << 16)
904 # define GEN8_RASTER_CULL_NONE                          (1 << 16)
905 # define GEN8_RASTER_CULL_FRONT                         (2 << 16)
906 # define GEN8_RASTER_CULL_BACK                          (3 << 16)
907 # define GEN8_RASTER_SMOOTH_POINT_ENABLE                (1 << 13)
908 # define GEN8_RASTER_API_MULTISAMPLE_ENABLE             (1 << 12)
909 # define GEN8_RASTER_LINE_AA_ENABLE                     (1 << 2)
910 # define GEN8_RASTER_SCISSOR_ENABLE                     (1 << 1)
911 # define GEN8_RASTER_VIEWPORT_Z_CLIP_TEST_ENABLE        (1 << 0)
912 # define GEN9_RASTER_VIEWPORT_Z_NEAR_CLIP_TEST_ENABLE   (1 << 0)
913 
914 /* Gen8 BLEND_STATE */
915 /* DW0 */
916 #define GEN8_BLEND_ALPHA_TO_COVERAGE_ENABLE             (1 << 31)
917 #define GEN8_BLEND_INDEPENDENT_ALPHA_BLEND_ENABLE       (1 << 30)
918 #define GEN8_BLEND_ALPHA_TO_ONE_ENABLE                  (1 << 29)
919 #define GEN8_BLEND_ALPHA_TO_COVERAGE_DITHER_ENABLE      (1 << 28)
920 #define GEN8_BLEND_ALPHA_TEST_ENABLE                    (1 << 27)
921 #define GEN8_BLEND_ALPHA_TEST_FUNCTION_MASK             INTEL_MASK(26, 24)
922 #define GEN8_BLEND_ALPHA_TEST_FUNCTION_SHIFT            24
923 #define GEN8_BLEND_COLOR_DITHER_ENABLE                  (1 << 23)
924 #define GEN8_BLEND_X_DITHER_OFFSET_MASK                 INTEL_MASK(22, 21)
925 #define GEN8_BLEND_X_DITHER_OFFSET_SHIFT                21
926 #define GEN8_BLEND_Y_DITHER_OFFSET_MASK                 INTEL_MASK(20, 19)
927 #define GEN8_BLEND_Y_DITHER_OFFSET_SHIFT                19
928 /* DW1 + 2n */
929 #define GEN8_BLEND_COLOR_BUFFER_BLEND_ENABLE            (1 << 31)
930 #define GEN8_BLEND_SRC_BLEND_FACTOR_MASK                INTEL_MASK(30, 26)
931 #define GEN8_BLEND_SRC_BLEND_FACTOR_SHIFT               26
932 #define GEN8_BLEND_DST_BLEND_FACTOR_MASK                INTEL_MASK(25, 21)
933 #define GEN8_BLEND_DST_BLEND_FACTOR_SHIFT               21
934 #define GEN8_BLEND_COLOR_BLEND_FUNCTION_MASK            INTEL_MASK(20, 18)
935 #define GEN8_BLEND_COLOR_BLEND_FUNCTION_SHIFT           18
936 #define GEN8_BLEND_SRC_ALPHA_BLEND_FACTOR_MASK          INTEL_MASK(17, 13)
937 #define GEN8_BLEND_SRC_ALPHA_BLEND_FACTOR_SHIFT         13
938 #define GEN8_BLEND_DST_ALPHA_BLEND_FACTOR_MASK          INTEL_MASK(12, 8)
939 #define GEN8_BLEND_DST_ALPHA_BLEND_FACTOR_SHIFT         8
940 #define GEN8_BLEND_ALPHA_BLEND_FUNCTION_MASK            INTEL_MASK(7, 5)
941 #define GEN8_BLEND_ALPHA_BLEND_FUNCTION_SHIFT           5
942 #define GEN8_BLEND_WRITE_DISABLE_ALPHA                  (1 << 3)
943 #define GEN8_BLEND_WRITE_DISABLE_RED                    (1 << 2)
944 #define GEN8_BLEND_WRITE_DISABLE_GREEN                  (1 << 1)
945 #define GEN8_BLEND_WRITE_DISABLE_BLUE                   (1 << 0)
946 /* DW1 + 2n + 1 */
947 #define GEN8_BLEND_LOGIC_OP_ENABLE                      (1 << 31)
948 #define GEN8_BLEND_LOGIC_OP_FUNCTION_MASK               INTEL_MASK(30, 27)
949 #define GEN8_BLEND_LOGIC_OP_FUNCTION_SHIFT              27
950 #define GEN8_BLEND_PRE_BLEND_SRC_ONLY_CLAMP_ENABLE      (1 << 4)
951 #define GEN8_BLEND_COLOR_CLAMP_RANGE_RTFORMAT           (2 << 2)
952 #define GEN8_BLEND_PRE_BLEND_COLOR_CLAMP_ENABLE         (1 << 1)
953 #define GEN8_BLEND_POST_BLEND_COLOR_CLAMP_ENABLE        (1 << 0)
954 
955 #define _3DSTATE_WM_HZ_OP                       0x7852 /* GEN8+ */
956 /* DW1 */
957 # define GEN8_WM_HZ_STENCIL_CLEAR                       (1 << 31)
958 # define GEN8_WM_HZ_DEPTH_CLEAR                         (1 << 30)
959 # define GEN8_WM_HZ_DEPTH_RESOLVE                       (1 << 28)
960 # define GEN8_WM_HZ_HIZ_RESOLVE                         (1 << 27)
961 # define GEN8_WM_HZ_PIXEL_OFFSET_ENABLE                 (1 << 26)
962 # define GEN8_WM_HZ_FULL_SURFACE_DEPTH_CLEAR            (1 << 25)
963 # define GEN8_WM_HZ_STENCIL_CLEAR_VALUE_MASK            INTEL_MASK(23, 16)
964 # define GEN8_WM_HZ_STENCIL_CLEAR_VALUE_SHIFT           16
965 # define GEN8_WM_HZ_NUM_SAMPLES_MASK                    INTEL_MASK(15, 13)
966 # define GEN8_WM_HZ_NUM_SAMPLES_SHIFT                   13
967 /* DW2 */
968 # define GEN8_WM_HZ_CLEAR_RECTANGLE_Y_MIN_MASK          INTEL_MASK(31, 16)
969 # define GEN8_WM_HZ_CLEAR_RECTANGLE_Y_MIN_SHIFT         16
970 # define GEN8_WM_HZ_CLEAR_RECTANGLE_X_MIN_MASK          INTEL_MASK(15, 0)
971 # define GEN8_WM_HZ_CLEAR_RECTANGLE_X_MIN_SHIFT         0
972 /* DW3 */
973 # define GEN8_WM_HZ_CLEAR_RECTANGLE_Y_MAX_MASK          INTEL_MASK(31, 16)
974 # define GEN8_WM_HZ_CLEAR_RECTANGLE_Y_MAX_SHIFT         16
975 # define GEN8_WM_HZ_CLEAR_RECTANGLE_X_MAX_MASK          INTEL_MASK(15, 0)
976 # define GEN8_WM_HZ_CLEAR_RECTANGLE_X_MAX_SHIFT         0
977 /* DW4 */
978 # define GEN8_WM_HZ_SAMPLE_MASK_MASK                    INTEL_MASK(15, 0)
979 # define GEN8_WM_HZ_SAMPLE_MASK_SHIFT                   0
980 
981 
982 #define _3DSTATE_PS_BLEND                       0x784D /* GEN8+ */
983 /* DW1 */
984 # define GEN8_PS_BLEND_ALPHA_TO_COVERAGE_ENABLE         (1 << 31)
985 # define GEN8_PS_BLEND_HAS_WRITEABLE_RT                 (1 << 30)
986 # define GEN8_PS_BLEND_COLOR_BUFFER_BLEND_ENABLE        (1 << 29)
987 # define GEN8_PS_BLEND_SRC_ALPHA_BLEND_FACTOR_MASK      INTEL_MASK(28, 24)
988 # define GEN8_PS_BLEND_SRC_ALPHA_BLEND_FACTOR_SHIFT     24
989 # define GEN8_PS_BLEND_DST_ALPHA_BLEND_FACTOR_MASK      INTEL_MASK(23, 19)
990 # define GEN8_PS_BLEND_DST_ALPHA_BLEND_FACTOR_SHIFT     19
991 # define GEN8_PS_BLEND_SRC_BLEND_FACTOR_MASK            INTEL_MASK(18, 14)
992 # define GEN8_PS_BLEND_SRC_BLEND_FACTOR_SHIFT           14
993 # define GEN8_PS_BLEND_DST_BLEND_FACTOR_MASK            INTEL_MASK(13, 9)
994 # define GEN8_PS_BLEND_DST_BLEND_FACTOR_SHIFT           9
995 # define GEN8_PS_BLEND_ALPHA_TEST_ENABLE                (1 << 8)
996 # define GEN8_PS_BLEND_INDEPENDENT_ALPHA_BLEND_ENABLE   (1 << 7)
997 
998 #define _3DSTATE_WM_DEPTH_STENCIL               0x784E /* GEN8+ */
999 /* DW1 */
1000 # define GEN8_WM_DS_STENCIL_FAIL_OP_SHIFT               29
1001 # define GEN8_WM_DS_Z_FAIL_OP_SHIFT                     26
1002 # define GEN8_WM_DS_Z_PASS_OP_SHIFT                     23
1003 # define GEN8_WM_DS_BF_STENCIL_FUNC_SHIFT               20
1004 # define GEN8_WM_DS_BF_STENCIL_FAIL_OP_SHIFT            17
1005 # define GEN8_WM_DS_BF_Z_FAIL_OP_SHIFT                  14
1006 # define GEN8_WM_DS_BF_Z_PASS_OP_SHIFT                  11
1007 # define GEN8_WM_DS_STENCIL_FUNC_SHIFT                  8
1008 # define GEN8_WM_DS_DEPTH_FUNC_SHIFT                    5
1009 # define GEN8_WM_DS_DOUBLE_SIDED_STENCIL_ENABLE         (1 << 4)
1010 # define GEN8_WM_DS_STENCIL_TEST_ENABLE                 (1 << 3)
1011 # define GEN8_WM_DS_STENCIL_BUFFER_WRITE_ENABLE         (1 << 2)
1012 # define GEN8_WM_DS_DEPTH_TEST_ENABLE                   (1 << 1)
1013 # define GEN8_WM_DS_DEPTH_BUFFER_WRITE_ENABLE           (1 << 0)
1014 /* DW2 */
1015 # define GEN8_WM_DS_STENCIL_TEST_MASK_MASK              INTEL_MASK(31, 24)
1016 # define GEN8_WM_DS_STENCIL_TEST_MASK_SHIFT             24
1017 # define GEN8_WM_DS_STENCIL_WRITE_MASK_MASK             INTEL_MASK(23, 16)
1018 # define GEN8_WM_DS_STENCIL_WRITE_MASK_SHIFT            16
1019 # define GEN8_WM_DS_BF_STENCIL_TEST_MASK_MASK           INTEL_MASK(15, 8)
1020 # define GEN8_WM_DS_BF_STENCIL_TEST_MASK_SHIFT          8
1021 # define GEN8_WM_DS_BF_STENCIL_WRITE_MASK_MASK          INTEL_MASK(7, 0)
1022 # define GEN8_WM_DS_BF_STENCIL_WRITE_MASK_SHIFT         0
1023 /* DW3 */
1024 # define GEN9_WM_DS_STENCIL_REF_MASK                    INTEL_MASK(15, 8)
1025 # define GEN9_WM_DS_STENCIL_REF_SHIFT                   8
1026 # define GEN9_WM_DS_BF_STENCIL_REF_MASK                 INTEL_MASK(7, 0)
1027 # define GEN9_WM_DS_BF_STENCIL_REF_SHIFT                0
1028 
1029 enum brw_pixel_shader_coverage_mask_mode {
1030    BRW_PSICMS_OFF     = 0, /* PS does not use input coverage masks. */
1031    BRW_PSICMS_NORMAL  = 1, /* Input Coverage masks based on outer conservatism
1032                             * and factors in SAMPLE_MASK.  If Pixel is
1033                             * conservatively covered, all samples are enabled.
1034                             */
1035 
1036    BRW_PSICMS_INNER   = 2, /* Input Coverage masks based on inner conservatism
1037                             * and factors in SAMPLE_MASK.  If Pixel is
1038                             * conservatively *FULLY* covered, all samples are
1039                             * enabled.
1040                             */
1041    BRW_PCICMS_DEPTH   = 3,
1042 };
1043 
1044 #define _3DSTATE_PS_EXTRA                       0x784F /* GEN8+ */
1045 /* DW1 */
1046 # define GEN8_PSX_PIXEL_SHADER_VALID                    (1 << 31)
1047 # define GEN8_PSX_PIXEL_SHADER_NO_RT_WRITE              (1 << 30)
1048 # define GEN8_PSX_OMASK_TO_RENDER_TARGET                (1 << 29)
1049 # define GEN8_PSX_KILL_ENABLE                           (1 << 28)
1050 # define GEN8_PSX_COMPUTED_DEPTH_MODE_SHIFT             26
1051 # define GEN8_PSX_FORCE_COMPUTED_DEPTH                  (1 << 25)
1052 # define GEN8_PSX_USES_SOURCE_DEPTH                     (1 << 24)
1053 # define GEN8_PSX_USES_SOURCE_W                         (1 << 23)
1054 # define GEN8_PSX_ATTRIBUTE_ENABLE                      (1 << 8)
1055 # define GEN8_PSX_SHADER_DISABLES_ALPHA_TO_COVERAGE     (1 << 7)
1056 # define GEN8_PSX_SHADER_IS_PER_SAMPLE                  (1 << 6)
1057 # define GEN9_PSX_SHADER_COMPUTES_STENCIL               (1 << 5)
1058 # define GEN9_PSX_SHADER_PULLS_BARY                     (1 << 3)
1059 # define GEN8_PSX_SHADER_HAS_UAV                        (1 << 2)
1060 # define GEN8_PSX_SHADER_USES_INPUT_COVERAGE_MASK       (1 << 1)
1061 # define GEN9_PSX_SHADER_NORMAL_COVERAGE_MASK_SHIFT     0
1062 
1063 #define _3DSTATE_WM				0x7814 /* GEN6+ */
1064 /* DW1: kernel pointer */
1065 /* DW2 */
1066 # define GEN6_WM_SPF_MODE				(1 << 31)
1067 # define GEN6_WM_VECTOR_MASK_ENABLE			(1 << 30)
1068 # define GEN6_WM_SAMPLER_COUNT_SHIFT			27
1069 # define GEN6_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT	18
1070 # define GEN6_WM_FLOATING_POINT_MODE_IEEE_754		(0 << 16)
1071 # define GEN6_WM_FLOATING_POINT_MODE_ALT		(1 << 16)
1072 /* DW3: scratch space */
1073 /* DW4 */
1074 # define GEN6_WM_STATISTICS_ENABLE			(1 << 31)
1075 # define GEN6_WM_DEPTH_CLEAR				(1 << 30)
1076 # define GEN6_WM_DEPTH_RESOLVE				(1 << 28)
1077 # define GEN6_WM_HIERARCHICAL_DEPTH_RESOLVE		(1 << 27)
1078 # define GEN6_WM_DISPATCH_START_GRF_SHIFT_0		16
1079 # define GEN6_WM_DISPATCH_START_GRF_SHIFT_1		8
1080 # define GEN6_WM_DISPATCH_START_GRF_SHIFT_2		0
1081 /* DW5 */
1082 # define GEN6_WM_MAX_THREADS_SHIFT			25
1083 # define GEN6_WM_KILL_ENABLE				(1 << 22)
1084 # define GEN6_WM_COMPUTED_DEPTH				(1 << 21)
1085 # define GEN6_WM_USES_SOURCE_DEPTH			(1 << 20)
1086 # define GEN6_WM_DISPATCH_ENABLE			(1 << 19)
1087 # define GEN6_WM_LINE_END_CAP_AA_WIDTH_0_5		(0 << 16)
1088 # define GEN6_WM_LINE_END_CAP_AA_WIDTH_1_0		(1 << 16)
1089 # define GEN6_WM_LINE_END_CAP_AA_WIDTH_2_0		(2 << 16)
1090 # define GEN6_WM_LINE_END_CAP_AA_WIDTH_4_0		(3 << 16)
1091 # define GEN6_WM_LINE_AA_WIDTH_0_5			(0 << 14)
1092 # define GEN6_WM_LINE_AA_WIDTH_1_0			(1 << 14)
1093 # define GEN6_WM_LINE_AA_WIDTH_2_0			(2 << 14)
1094 # define GEN6_WM_LINE_AA_WIDTH_4_0			(3 << 14)
1095 # define GEN6_WM_POLYGON_STIPPLE_ENABLE			(1 << 13)
1096 # define GEN6_WM_LINE_STIPPLE_ENABLE			(1 << 11)
1097 # define GEN6_WM_OMASK_TO_RENDER_TARGET			(1 << 9)
1098 # define GEN6_WM_USES_SOURCE_W				(1 << 8)
1099 # define GEN6_WM_DUAL_SOURCE_BLEND_ENABLE		(1 << 7)
1100 # define GEN6_WM_32_DISPATCH_ENABLE			(1 << 2)
1101 # define GEN6_WM_16_DISPATCH_ENABLE			(1 << 1)
1102 # define GEN6_WM_8_DISPATCH_ENABLE			(1 << 0)
1103 /* DW6 */
1104 # define GEN6_WM_NUM_SF_OUTPUTS_SHIFT			20
1105 # define GEN6_WM_POSOFFSET_NONE				(0 << 18)
1106 # define GEN6_WM_POSOFFSET_CENTROID			(2 << 18)
1107 # define GEN6_WM_POSOFFSET_SAMPLE			(3 << 18)
1108 # define GEN6_WM_POSITION_ZW_PIXEL			(0 << 16)
1109 # define GEN6_WM_POSITION_ZW_CENTROID			(2 << 16)
1110 # define GEN6_WM_POSITION_ZW_SAMPLE			(3 << 16)
1111 # define GEN6_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC	(1 << 15)
1112 # define GEN6_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC	(1 << 14)
1113 # define GEN6_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC	(1 << 13)
1114 # define GEN6_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC		(1 << 12)
1115 # define GEN6_WM_PERSPECTIVE_CENTROID_BARYCENTRIC	(1 << 11)
1116 # define GEN6_WM_PERSPECTIVE_PIXEL_BARYCENTRIC		(1 << 10)
1117 # define GEN6_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT   10
1118 # define GEN6_WM_POINT_RASTRULE_UPPER_RIGHT		(1 << 9)
1119 # define GEN6_WM_MSRAST_OFF_PIXEL			(0 << 1)
1120 # define GEN6_WM_MSRAST_OFF_PATTERN			(1 << 1)
1121 # define GEN6_WM_MSRAST_ON_PIXEL			(2 << 1)
1122 # define GEN6_WM_MSRAST_ON_PATTERN			(3 << 1)
1123 # define GEN6_WM_MSDISPMODE_PERSAMPLE			(0 << 0)
1124 # define GEN6_WM_MSDISPMODE_PERPIXEL			(1 << 0)
1125 /* DW7: kernel 1 pointer */
1126 /* DW8: kernel 2 pointer */
1127 
1128 #define _3DSTATE_CONSTANT_VS		      0x7815 /* GEN6+ */
1129 #define _3DSTATE_CONSTANT_GS		      0x7816 /* GEN6+ */
1130 #define _3DSTATE_CONSTANT_PS		      0x7817 /* GEN6+ */
1131 # define GEN6_CONSTANT_BUFFER_3_ENABLE			(1 << 15)
1132 # define GEN6_CONSTANT_BUFFER_2_ENABLE			(1 << 14)
1133 # define GEN6_CONSTANT_BUFFER_1_ENABLE			(1 << 13)
1134 # define GEN6_CONSTANT_BUFFER_0_ENABLE			(1 << 12)
1135 
1136 #define _3DSTATE_CONSTANT_HS                  0x7819 /* GEN7+ */
1137 #define _3DSTATE_CONSTANT_DS                  0x781A /* GEN7+ */
1138 
1139 #define _3DSTATE_STREAMOUT                    0x781e /* GEN7+ */
1140 /* DW1 */
1141 # define SO_FUNCTION_ENABLE				(1 << 31)
1142 # define SO_RENDERING_DISABLE				(1 << 30)
1143 /* This selects which incoming rendering stream goes down the pipeline.  The
1144  * rendering stream is 0 if not defined by special cases in the GS state.
1145  */
1146 # define SO_RENDER_STREAM_SELECT_SHIFT			27
1147 # define SO_RENDER_STREAM_SELECT_MASK			INTEL_MASK(28, 27)
1148 /* Controls reordering of TRISTRIP_* elements in stream output (not rendering).
1149  */
1150 # define SO_REORDER_TRAILING				(1 << 26)
1151 /* Controls SO_NUM_PRIMS_WRITTEN_* and SO_PRIM_STORAGE_* */
1152 # define SO_STATISTICS_ENABLE				(1 << 25)
1153 # define SO_BUFFER_ENABLE(n)				(1 << (8 + (n)))
1154 /* DW2 */
1155 # define SO_STREAM_3_VERTEX_READ_OFFSET_SHIFT		29
1156 # define SO_STREAM_3_VERTEX_READ_OFFSET_MASK		INTEL_MASK(29, 29)
1157 # define SO_STREAM_3_VERTEX_READ_LENGTH_SHIFT		24
1158 # define SO_STREAM_3_VERTEX_READ_LENGTH_MASK		INTEL_MASK(28, 24)
1159 # define SO_STREAM_2_VERTEX_READ_OFFSET_SHIFT		21
1160 # define SO_STREAM_2_VERTEX_READ_OFFSET_MASK		INTEL_MASK(21, 21)
1161 # define SO_STREAM_2_VERTEX_READ_LENGTH_SHIFT		16
1162 # define SO_STREAM_2_VERTEX_READ_LENGTH_MASK		INTEL_MASK(20, 16)
1163 # define SO_STREAM_1_VERTEX_READ_OFFSET_SHIFT		13
1164 # define SO_STREAM_1_VERTEX_READ_OFFSET_MASK		INTEL_MASK(13, 13)
1165 # define SO_STREAM_1_VERTEX_READ_LENGTH_SHIFT		8
1166 # define SO_STREAM_1_VERTEX_READ_LENGTH_MASK		INTEL_MASK(12, 8)
1167 # define SO_STREAM_0_VERTEX_READ_OFFSET_SHIFT		5
1168 # define SO_STREAM_0_VERTEX_READ_OFFSET_MASK		INTEL_MASK(5, 5)
1169 # define SO_STREAM_0_VERTEX_READ_LENGTH_SHIFT		0
1170 # define SO_STREAM_0_VERTEX_READ_LENGTH_MASK		INTEL_MASK(4, 0)
1171 
1172 /* 3DSTATE_WM for Gen7 */
1173 /* DW1 */
1174 # define GEN7_WM_STATISTICS_ENABLE			(1 << 31)
1175 # define GEN7_WM_DEPTH_CLEAR				(1 << 30)
1176 # define GEN7_WM_DISPATCH_ENABLE			(1 << 29)
1177 # define GEN7_WM_DEPTH_RESOLVE				(1 << 28)
1178 # define GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE		(1 << 27)
1179 # define GEN7_WM_KILL_ENABLE				(1 << 25)
1180 # define GEN7_WM_COMPUTED_DEPTH_MODE_SHIFT              23
1181 # define GEN7_WM_USES_SOURCE_DEPTH			(1 << 20)
1182 # define GEN7_WM_EARLY_DS_CONTROL_NORMAL                (0 << 21)
1183 # define GEN7_WM_EARLY_DS_CONTROL_PSEXEC                (1 << 21)
1184 # define GEN7_WM_EARLY_DS_CONTROL_PREPS                 (2 << 21)
1185 # define GEN7_WM_USES_SOURCE_W			        (1 << 19)
1186 # define GEN7_WM_POSITION_ZW_PIXEL			(0 << 17)
1187 # define GEN7_WM_POSITION_ZW_CENTROID			(2 << 17)
1188 # define GEN7_WM_POSITION_ZW_SAMPLE			(3 << 17)
1189 # define GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT   11
1190 # define GEN7_WM_USES_INPUT_COVERAGE_MASK	        (1 << 10)
1191 # define GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5		(0 << 8)
1192 # define GEN7_WM_LINE_END_CAP_AA_WIDTH_1_0		(1 << 8)
1193 # define GEN7_WM_LINE_END_CAP_AA_WIDTH_2_0		(2 << 8)
1194 # define GEN7_WM_LINE_END_CAP_AA_WIDTH_4_0		(3 << 8)
1195 # define GEN7_WM_LINE_AA_WIDTH_0_5			(0 << 6)
1196 # define GEN7_WM_LINE_AA_WIDTH_1_0			(1 << 6)
1197 # define GEN7_WM_LINE_AA_WIDTH_2_0			(2 << 6)
1198 # define GEN7_WM_LINE_AA_WIDTH_4_0			(3 << 6)
1199 # define GEN7_WM_POLYGON_STIPPLE_ENABLE			(1 << 4)
1200 # define GEN7_WM_LINE_STIPPLE_ENABLE			(1 << 3)
1201 # define GEN7_WM_POINT_RASTRULE_UPPER_RIGHT		(1 << 2)
1202 # define GEN7_WM_MSRAST_OFF_PIXEL			(0 << 0)
1203 # define GEN7_WM_MSRAST_OFF_PATTERN			(1 << 0)
1204 # define GEN7_WM_MSRAST_ON_PIXEL			(2 << 0)
1205 # define GEN7_WM_MSRAST_ON_PATTERN			(3 << 0)
1206 /* DW2 */
1207 # define GEN7_WM_MSDISPMODE_PERSAMPLE			(0 << 31)
1208 # define GEN7_WM_MSDISPMODE_PERPIXEL			(1 << 31)
1209 # define HSW_WM_UAV_ONLY                                (1 << 30)
1210 
1211 #define _3DSTATE_PS				0x7820 /* GEN7+ */
1212 /* DW1: kernel pointer */
1213 /* DW2 */
1214 # define GEN7_PS_SPF_MODE				(1 << 31)
1215 # define GEN7_PS_VECTOR_MASK_ENABLE			(1 << 30)
1216 # define GEN7_PS_SAMPLER_COUNT_SHIFT			27
1217 # define GEN7_PS_SAMPLER_COUNT_MASK                     INTEL_MASK(29, 27)
1218 # define GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT	18
1219 # define GEN7_PS_FLOATING_POINT_MODE_IEEE_754		(0 << 16)
1220 # define GEN7_PS_FLOATING_POINT_MODE_ALT		(1 << 16)
1221 /* DW3: scratch space */
1222 /* DW4 */
1223 # define IVB_PS_MAX_THREADS_SHIFT			24
1224 # define HSW_PS_MAX_THREADS_SHIFT			23
1225 # define HSW_PS_SAMPLE_MASK_SHIFT		        12
1226 # define HSW_PS_SAMPLE_MASK_MASK			INTEL_MASK(19, 12)
1227 # define GEN7_PS_PUSH_CONSTANT_ENABLE		        (1 << 11)
1228 # define GEN7_PS_ATTRIBUTE_ENABLE		        (1 << 10)
1229 # define GEN7_PS_OMASK_TO_RENDER_TARGET			(1 << 9)
1230 # define GEN7_PS_RENDER_TARGET_FAST_CLEAR_ENABLE	(1 << 8)
1231 # define GEN7_PS_DUAL_SOURCE_BLEND_ENABLE		(1 << 7)
1232 # define GEN7_PS_RENDER_TARGET_RESOLVE_ENABLE		(1 << 6)
1233 # define GEN9_PS_RENDER_TARGET_RESOLVE_FULL             (3 << 6)
1234 # define HSW_PS_UAV_ACCESS_ENABLE			(1 << 5)
1235 # define GEN7_PS_POSOFFSET_NONE				(0 << 3)
1236 # define GEN7_PS_POSOFFSET_CENTROID			(2 << 3)
1237 # define GEN7_PS_POSOFFSET_SAMPLE			(3 << 3)
1238 # define GEN7_PS_32_DISPATCH_ENABLE			(1 << 2)
1239 # define GEN7_PS_16_DISPATCH_ENABLE			(1 << 1)
1240 # define GEN7_PS_8_DISPATCH_ENABLE			(1 << 0)
1241 /* DW5 */
1242 # define GEN7_PS_DISPATCH_START_GRF_SHIFT_0		16
1243 # define GEN7_PS_DISPATCH_START_GRF_SHIFT_1		8
1244 # define GEN7_PS_DISPATCH_START_GRF_SHIFT_2		0
1245 /* DW6: kernel 1 pointer */
1246 /* DW7: kernel 2 pointer */
1247 
1248 #define _3DSTATE_SAMPLE_MASK			0x7818 /* GEN6+ */
1249 
1250 #define _3DSTATE_DRAWING_RECTANGLE		0x7900
1251 #define _3DSTATE_BLEND_CONSTANT_COLOR		0x7901
1252 #define _3DSTATE_CHROMA_KEY			0x7904
1253 #define _3DSTATE_DEPTH_BUFFER			0x7905 /* GEN4-6 */
1254 #define _3DSTATE_POLY_STIPPLE_OFFSET		0x7906
1255 #define _3DSTATE_POLY_STIPPLE_PATTERN		0x7907
1256 #define _3DSTATE_LINE_STIPPLE_PATTERN		0x7908
1257 #define _3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP	0x7909
1258 #define _3DSTATE_AA_LINE_PARAMETERS		0x790a /* G45+ */
1259 
1260 #define _3DSTATE_GS_SVB_INDEX			0x790b /* CTG+ */
1261 /* DW1 */
1262 # define SVB_INDEX_SHIFT				29
1263 # define SVB_LOAD_INTERNAL_VERTEX_COUNT			(1 << 0) /* SNB+ */
1264 /* DW2: SVB index */
1265 /* DW3: SVB maximum index */
1266 
1267 #define _3DSTATE_MULTISAMPLE			0x790d /* GEN6+ */
1268 #define GEN8_3DSTATE_MULTISAMPLE		0x780d /* GEN8+ */
1269 /* DW1 */
1270 # define MS_PIXEL_LOCATION_CENTER			(0 << 4)
1271 # define MS_PIXEL_LOCATION_UPPER_LEFT			(1 << 4)
1272 # define MS_NUMSAMPLES_1				(0 << 1)
1273 # define MS_NUMSAMPLES_2				(1 << 1)
1274 # define MS_NUMSAMPLES_4				(2 << 1)
1275 # define MS_NUMSAMPLES_8				(3 << 1)
1276 # define MS_NUMSAMPLES_16				(4 << 1)
1277 
1278 #define _3DSTATE_SAMPLE_PATTERN                 0x791c
1279 
1280 #define _3DSTATE_STENCIL_BUFFER			0x790e /* ILK, SNB */
1281 #define _3DSTATE_HIER_DEPTH_BUFFER		0x790f /* ILK, SNB */
1282 
1283 #define GEN7_3DSTATE_CLEAR_PARAMS		0x7804
1284 #define GEN7_3DSTATE_DEPTH_BUFFER		0x7805
1285 #define GEN7_3DSTATE_STENCIL_BUFFER		0x7806
1286 # define HSW_STENCIL_ENABLED                            (1 << 31)
1287 #define GEN7_3DSTATE_HIER_DEPTH_BUFFER		0x7807
1288 
1289 #define _3DSTATE_CLEAR_PARAMS			0x7910 /* ILK, SNB */
1290 # define GEN5_DEPTH_CLEAR_VALID				(1 << 15)
1291 /* DW1: depth clear value */
1292 /* DW2 */
1293 # define GEN7_DEPTH_CLEAR_VALID				(1 << 0)
1294 
1295 #define _3DSTATE_SO_DECL_LIST			0x7917 /* GEN7+ */
1296 /* DW1 */
1297 # define SO_STREAM_TO_BUFFER_SELECTS_3_SHIFT		12
1298 # define SO_STREAM_TO_BUFFER_SELECTS_3_MASK		INTEL_MASK(15, 12)
1299 # define SO_STREAM_TO_BUFFER_SELECTS_2_SHIFT		8
1300 # define SO_STREAM_TO_BUFFER_SELECTS_2_MASK		INTEL_MASK(11, 8)
1301 # define SO_STREAM_TO_BUFFER_SELECTS_1_SHIFT		4
1302 # define SO_STREAM_TO_BUFFER_SELECTS_1_MASK		INTEL_MASK(7, 4)
1303 # define SO_STREAM_TO_BUFFER_SELECTS_0_SHIFT		0
1304 # define SO_STREAM_TO_BUFFER_SELECTS_0_MASK		INTEL_MASK(3, 0)
1305 /* DW2 */
1306 # define SO_NUM_ENTRIES_3_SHIFT				24
1307 # define SO_NUM_ENTRIES_3_MASK				INTEL_MASK(31, 24)
1308 # define SO_NUM_ENTRIES_2_SHIFT				16
1309 # define SO_NUM_ENTRIES_2_MASK				INTEL_MASK(23, 16)
1310 # define SO_NUM_ENTRIES_1_SHIFT				8
1311 # define SO_NUM_ENTRIES_1_MASK				INTEL_MASK(15, 8)
1312 # define SO_NUM_ENTRIES_0_SHIFT				0
1313 # define SO_NUM_ENTRIES_0_MASK				INTEL_MASK(7, 0)
1314 
1315 /* SO_DECL DW0 */
1316 # define SO_DECL_OUTPUT_BUFFER_SLOT_SHIFT		12
1317 # define SO_DECL_OUTPUT_BUFFER_SLOT_MASK		INTEL_MASK(13, 12)
1318 # define SO_DECL_HOLE_FLAG				(1 << 11)
1319 # define SO_DECL_REGISTER_INDEX_SHIFT			4
1320 # define SO_DECL_REGISTER_INDEX_MASK			INTEL_MASK(9, 4)
1321 # define SO_DECL_COMPONENT_MASK_SHIFT			0
1322 # define SO_DECL_COMPONENT_MASK_MASK			INTEL_MASK(3, 0)
1323 
1324 #define _3DSTATE_SO_BUFFER                    0x7918 /* GEN7+ */
1325 /* DW1 */
1326 # define GEN8_SO_BUFFER_ENABLE                          (1 << 31)
1327 # define SO_BUFFER_INDEX_SHIFT				29
1328 # define SO_BUFFER_INDEX_MASK				INTEL_MASK(30, 29)
1329 # define GEN8_SO_BUFFER_OFFSET_WRITE_ENABLE             (1 << 21)
1330 # define GEN8_SO_BUFFER_OFFSET_ADDRESS_ENABLE           (1 << 20)
1331 # define SO_BUFFER_PITCH_SHIFT				0
1332 # define SO_BUFFER_PITCH_MASK				INTEL_MASK(11, 0)
1333 /* DW2: start address */
1334 /* DW3: end address. */
1335 
1336 #define _3DSTATE_3D_MODE                     0x791e
1337 
1338 #define CMD_MI_FLUSH                  0x0200
1339 
1340 # define BLT_X_SHIFT					0
1341 # define BLT_X_MASK					INTEL_MASK(15, 0)
1342 # define BLT_Y_SHIFT					16
1343 # define BLT_Y_MASK					INTEL_MASK(31, 16)
1344 
1345 #define GEN5_MI_REPORT_PERF_COUNT ((0x26 << 23) | (3 - 2))
1346 /* DW0 */
1347 # define GEN5_MI_COUNTER_SET_0      (0 << 6)
1348 # define GEN5_MI_COUNTER_SET_1      (1 << 6)
1349 /* DW1 */
1350 # define MI_COUNTER_ADDRESS_GTT     (1 << 0)
1351 /* DW2: a user-defined report ID (written to the buffer but can be anything) */
1352 
1353 #define GEN6_MI_REPORT_PERF_COUNT ((0x28 << 23) | (3 - 2))
1354 
1355 #define GEN8_MI_REPORT_PERF_COUNT ((0x28 << 23) | (4 - 2))
1356 
1357 /* Maximum number of entries that can be addressed using a binding table
1358  * pointer of type SURFTYPE_BUFFER
1359  */
1360 #define BRW_MAX_NUM_BUFFER_ENTRIES	(1 << 27)
1361 
1362 #define MEDIA_VFE_STATE                         0x7000
1363 /* GEN7 DW2, GEN8+ DW3 */
1364 # define MEDIA_VFE_STATE_MAX_THREADS_SHIFT      16
1365 # define MEDIA_VFE_STATE_MAX_THREADS_MASK       INTEL_MASK(31, 16)
1366 # define MEDIA_VFE_STATE_URB_ENTRIES_SHIFT      8
1367 # define MEDIA_VFE_STATE_URB_ENTRIES_MASK       INTEL_MASK(15, 8)
1368 # define MEDIA_VFE_STATE_RESET_GTW_TIMER_SHIFT  7
1369 # define MEDIA_VFE_STATE_RESET_GTW_TIMER_MASK   INTEL_MASK(7, 7)
1370 # define MEDIA_VFE_STATE_BYPASS_GTW_SHIFT       6
1371 # define MEDIA_VFE_STATE_BYPASS_GTW_MASK        INTEL_MASK(6, 6)
1372 # define GEN7_MEDIA_VFE_STATE_GPGPU_MODE_SHIFT  2
1373 # define GEN7_MEDIA_VFE_STATE_GPGPU_MODE_MASK   INTEL_MASK(2, 2)
1374 /* GEN7 DW4, GEN8+ DW5 */
1375 # define MEDIA_VFE_STATE_URB_ALLOC_SHIFT        16
1376 # define MEDIA_VFE_STATE_URB_ALLOC_MASK         INTEL_MASK(31, 16)
1377 # define MEDIA_VFE_STATE_CURBE_ALLOC_SHIFT      0
1378 # define MEDIA_VFE_STATE_CURBE_ALLOC_MASK       INTEL_MASK(15, 0)
1379 
1380 #define MEDIA_CURBE_LOAD                        0x7001
1381 #define MEDIA_INTERFACE_DESCRIPTOR_LOAD         0x7002
1382 /* GEN7 DW4, GEN8+ DW5 */
1383 # define MEDIA_CURBE_READ_LENGTH_SHIFT          16
1384 # define MEDIA_CURBE_READ_LENGTH_MASK           INTEL_MASK(31, 16)
1385 # define MEDIA_CURBE_READ_OFFSET_SHIFT          0
1386 # define MEDIA_CURBE_READ_OFFSET_MASK           INTEL_MASK(15, 0)
1387 /* GEN7 DW5, GEN8+ DW6 */
1388 # define MEDIA_BARRIER_ENABLE_SHIFT             21
1389 # define MEDIA_BARRIER_ENABLE_MASK              INTEL_MASK(21, 21)
1390 # define MEDIA_SHARED_LOCAL_MEMORY_SIZE_SHIFT   16
1391 # define MEDIA_SHARED_LOCAL_MEMORY_SIZE_MASK    INTEL_MASK(20, 16)
1392 # define MEDIA_GPGPU_THREAD_COUNT_SHIFT         0
1393 # define MEDIA_GPGPU_THREAD_COUNT_MASK          INTEL_MASK(7, 0)
1394 # define GEN8_MEDIA_GPGPU_THREAD_COUNT_SHIFT    0
1395 # define GEN8_MEDIA_GPGPU_THREAD_COUNT_MASK     INTEL_MASK(9, 0)
1396 /* GEN7 DW6, GEN8+ DW7 */
1397 # define CROSS_THREAD_READ_LENGTH_SHIFT         0
1398 # define CROSS_THREAD_READ_LENGTH_MASK          INTEL_MASK(7, 0)
1399 #define MEDIA_STATE_FLUSH                       0x7004
1400 #define GPGPU_WALKER                            0x7105
1401 /* GEN7 DW0 */
1402 # define GEN7_GPGPU_INDIRECT_PARAMETER_ENABLE   (1 << 10)
1403 # define GEN7_GPGPU_PREDICATE_ENABLE            (1 << 8)
1404 /* GEN8+ DW2 */
1405 # define GPGPU_WALKER_INDIRECT_LENGTH_SHIFT     0
1406 # define GPGPU_WALKER_INDIRECT_LENGTH_MASK      INTEL_MASK(15, 0)
1407 /* GEN7 DW2, GEN8+ DW4 */
1408 # define GPGPU_WALKER_SIMD_SIZE_SHIFT           30
1409 # define GPGPU_WALKER_SIMD_SIZE_MASK            INTEL_MASK(31, 30)
1410 # define GPGPU_WALKER_THREAD_DEPTH_MAX_SHIFT    16
1411 # define GPGPU_WALKER_THREAD_DEPTH_MAX_MASK     INTEL_MASK(21, 16)
1412 # define GPGPU_WALKER_THREAD_HEIGHT_MAX_SHIFT   8
1413 # define GPGPU_WALKER_THREAD_HEIGHT_MAX_MASK    INTEL_MASK(31, 8)
1414 # define GPGPU_WALKER_THREAD_WIDTH_MAX_SHIFT    0
1415 # define GPGPU_WALKER_THREAD_WIDTH_MAX_MASK     INTEL_MASK(5, 0)
1416 
1417 #define CMD_MI				(0x0 << 29)
1418 #define CMD_2D				(0x2 << 29)
1419 #define CMD_3D				(0x3 << 29)
1420 
1421 #define MI_NOOP				(CMD_MI | 0)
1422 
1423 #define MI_BATCH_BUFFER_END		(CMD_MI | 0xA << 23)
1424 
1425 #define MI_FLUSH			(CMD_MI | (4 << 23))
1426 #define FLUSH_MAP_CACHE				(1 << 0)
1427 #define INHIBIT_FLUSH_RENDER_CACHE		(1 << 2)
1428 
1429 #define MI_STORE_DATA_IMM		(CMD_MI | (0x20 << 23))
1430 #define MI_LOAD_REGISTER_IMM		(CMD_MI | (0x22 << 23))
1431 #define MI_LOAD_REGISTER_REG		(CMD_MI | (0x2A << 23))
1432 
1433 #define MI_FLUSH_DW			(CMD_MI | (0x26 << 23))
1434 
1435 #define MI_STORE_REGISTER_MEM		(CMD_MI | (0x24 << 23))
1436 # define MI_STORE_REGISTER_MEM_USE_GGTT		(1 << 22)
1437 # define MI_STORE_REGISTER_MEM_PREDICATE	(1 << 21)
1438 
1439 /* Load a value from memory into a register.  Only available on Gen7+. */
1440 #define GEN7_MI_LOAD_REGISTER_MEM	(CMD_MI | (0x29 << 23))
1441 # define MI_LOAD_REGISTER_MEM_USE_GGTT		(1 << 22)
1442 
1443 /* Manipulate the predicate bit based on some register values. Only on Gen7+ */
1444 #define GEN7_MI_PREDICATE		(CMD_MI | (0xC << 23))
1445 # define MI_PREDICATE_LOADOP_KEEP		(0 << 6)
1446 # define MI_PREDICATE_LOADOP_LOAD		(2 << 6)
1447 # define MI_PREDICATE_LOADOP_LOADINV		(3 << 6)
1448 # define MI_PREDICATE_COMBINEOP_SET		(0 << 3)
1449 # define MI_PREDICATE_COMBINEOP_AND		(1 << 3)
1450 # define MI_PREDICATE_COMBINEOP_OR		(2 << 3)
1451 # define MI_PREDICATE_COMBINEOP_XOR		(3 << 3)
1452 # define MI_PREDICATE_COMPAREOP_TRUE		(0 << 0)
1453 # define MI_PREDICATE_COMPAREOP_FALSE		(1 << 0)
1454 # define MI_PREDICATE_COMPAREOP_SRCS_EQUAL	(2 << 0)
1455 # define MI_PREDICATE_COMPAREOP_DELTAS_EQUAL	(3 << 0)
1456 
1457 #define HSW_MI_MATH			(CMD_MI | (0x1a << 23))
1458 
1459 #define MI_MATH_ALU2(opcode, operand1, operand2) \
1460    ( ((MI_MATH_OPCODE_##opcode) << 20) | ((MI_MATH_OPERAND_##operand1) << 10) | \
1461      ((MI_MATH_OPERAND_##operand2) << 0) )
1462 
1463 #define MI_MATH_ALU1(opcode, operand1) \
1464    ( ((MI_MATH_OPCODE_##opcode) << 20) | ((MI_MATH_OPERAND_##operand1) << 10) )
1465 
1466 #define MI_MATH_ALU0(opcode) \
1467    ( ((MI_MATH_OPCODE_##opcode) << 20) )
1468 
1469 #define MI_MATH_OPCODE_NOOP      0x000
1470 #define MI_MATH_OPCODE_LOAD      0x080
1471 #define MI_MATH_OPCODE_LOADINV   0x480
1472 #define MI_MATH_OPCODE_LOAD0     0x081
1473 #define MI_MATH_OPCODE_LOAD1     0x481
1474 #define MI_MATH_OPCODE_ADD       0x100
1475 #define MI_MATH_OPCODE_SUB       0x101
1476 #define MI_MATH_OPCODE_AND       0x102
1477 #define MI_MATH_OPCODE_OR        0x103
1478 #define MI_MATH_OPCODE_XOR       0x104
1479 #define MI_MATH_OPCODE_STORE     0x180
1480 #define MI_MATH_OPCODE_STOREINV  0x580
1481 
1482 #define MI_MATH_OPERAND_R0   0x00
1483 #define MI_MATH_OPERAND_R1   0x01
1484 #define MI_MATH_OPERAND_R2   0x02
1485 #define MI_MATH_OPERAND_R3   0x03
1486 #define MI_MATH_OPERAND_R4   0x04
1487 #define MI_MATH_OPERAND_SRCA 0x20
1488 #define MI_MATH_OPERAND_SRCB 0x21
1489 #define MI_MATH_OPERAND_ACCU 0x31
1490 #define MI_MATH_OPERAND_ZF   0x32
1491 #define MI_MATH_OPERAND_CF   0x33
1492 
1493 #define XY_SETUP_BLT_CMD		(CMD_2D | (0x01 << 22))
1494 
1495 #define XY_COLOR_BLT_CMD		(CMD_2D | (0x50 << 22))
1496 
1497 #define XY_SRC_COPY_BLT_CMD             (CMD_2D | (0x53 << 22))
1498 
1499 #define XY_FAST_COPY_BLT_CMD             (CMD_2D | (0x42 << 22))
1500 
1501 #define XY_TEXT_IMMEDIATE_BLIT_CMD	(CMD_2D | (0x31 << 22))
1502 # define XY_TEXT_BYTE_PACKED		(1 << 16)
1503 
1504 /* BR00 */
1505 #define XY_BLT_WRITE_ALPHA	(1 << 21)
1506 #define XY_BLT_WRITE_RGB	(1 << 20)
1507 #define XY_SRC_TILED		(1 << 15)
1508 #define XY_DST_TILED		(1 << 11)
1509 
1510 /* BR00 */
1511 #define XY_FAST_SRC_TILED_64K        (3 << 20)
1512 #define XY_FAST_SRC_TILED_Y          (2 << 20)
1513 #define XY_FAST_SRC_TILED_X          (1 << 20)
1514 
1515 #define XY_FAST_DST_TILED_64K        (3 << 13)
1516 #define XY_FAST_DST_TILED_Y          (2 << 13)
1517 #define XY_FAST_DST_TILED_X          (1 << 13)
1518 
1519 /* BR13 */
1520 #define BR13_8			(0x0 << 24)
1521 #define BR13_565		(0x1 << 24)
1522 #define BR13_8888		(0x3 << 24)
1523 #define BR13_16161616		(0x4 << 24)
1524 #define BR13_32323232		(0x5 << 24)
1525 
1526 /* Pipeline Statistics Counter Registers */
1527 #define IA_VERTICES_COUNT               0x2310
1528 #define IA_PRIMITIVES_COUNT             0x2318
1529 #define VS_INVOCATION_COUNT             0x2320
1530 #define HS_INVOCATION_COUNT             0x2300
1531 #define DS_INVOCATION_COUNT             0x2308
1532 #define GS_INVOCATION_COUNT             0x2328
1533 #define GS_PRIMITIVES_COUNT             0x2330
1534 #define CL_INVOCATION_COUNT             0x2338
1535 #define CL_PRIMITIVES_COUNT             0x2340
1536 #define PS_INVOCATION_COUNT             0x2348
1537 #define CS_INVOCATION_COUNT             0x2290
1538 #define PS_DEPTH_COUNT                  0x2350
1539 
1540 #define GEN6_SO_PRIM_STORAGE_NEEDED     0x2280
1541 #define GEN7_SO_PRIM_STORAGE_NEEDED(n)  (0x5240 + (n) * 8)
1542 
1543 #define GEN6_SO_NUM_PRIMS_WRITTEN       0x2288
1544 #define GEN7_SO_NUM_PRIMS_WRITTEN(n)    (0x5200 + (n) * 8)
1545 
1546 #define GEN7_SO_WRITE_OFFSET(n)         (0x5280 + (n) * 4)
1547 
1548 #define TIMESTAMP                       0x2358
1549 
1550 #define BCS_SWCTRL                      0x22200
1551 # define BCS_SWCTRL_SRC_Y               (1 << 0)
1552 # define BCS_SWCTRL_DST_Y               (1 << 1)
1553 
1554 #define OACONTROL                       0x2360
1555 # define OACONTROL_COUNTER_SELECT_SHIFT  2
1556 # define OACONTROL_ENABLE_COUNTERS       (1 << 0)
1557 
1558 /* Auto-Draw / Indirect Registers */
1559 #define GEN7_3DPRIM_END_OFFSET          0x2420
1560 #define GEN7_3DPRIM_START_VERTEX        0x2430
1561 #define GEN7_3DPRIM_VERTEX_COUNT        0x2434
1562 #define GEN7_3DPRIM_INSTANCE_COUNT      0x2438
1563 #define GEN7_3DPRIM_START_INSTANCE      0x243C
1564 #define GEN7_3DPRIM_BASE_VERTEX         0x2440
1565 
1566 /* Auto-Compute / Indirect Registers */
1567 #define GEN7_GPGPU_DISPATCHDIMX         0x2500
1568 #define GEN7_GPGPU_DISPATCHDIMY         0x2504
1569 #define GEN7_GPGPU_DISPATCHDIMZ         0x2508
1570 
1571 #define GEN7_CACHE_MODE_0               0x7000
1572 #define GEN7_CACHE_MODE_1               0x7004
1573 # define GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 4)
1574 # define GEN8_HIZ_NP_PMA_FIX_ENABLE        (1 << 11)
1575 # define GEN8_HIZ_NP_EARLY_Z_FAILS_DISABLE (1 << 13)
1576 # define GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC (1 << 1)
1577 # define GEN8_HIZ_PMA_MASK_BITS \
1578    REG_MASK(GEN8_HIZ_NP_PMA_FIX_ENABLE | GEN8_HIZ_NP_EARLY_Z_FAILS_DISABLE)
1579 
1580 #define GEN7_GT_MODE                    0x7008
1581 # define GEN9_SUBSLICE_HASHING_8x8      (0 << 8)
1582 # define GEN9_SUBSLICE_HASHING_16x4     (1 << 8)
1583 # define GEN9_SUBSLICE_HASHING_8x4      (2 << 8)
1584 # define GEN9_SUBSLICE_HASHING_16x16    (3 << 8)
1585 # define GEN9_SUBSLICE_HASHING_MASK_BITS REG_MASK(3 << 8)
1586 
1587 /* Predicate registers */
1588 #define MI_PREDICATE_SRC0               0x2400
1589 #define MI_PREDICATE_SRC1               0x2408
1590 #define MI_PREDICATE_DATA               0x2410
1591 #define MI_PREDICATE_RESULT             0x2418
1592 #define MI_PREDICATE_RESULT_1           0x241C
1593 #define MI_PREDICATE_RESULT_2           0x2214
1594 
1595 #define HSW_CS_GPR(n) (0x2600 + (n) * 8)
1596 
1597 /* L3 cache control registers. */
1598 #define GEN7_L3SQCREG1                     0xb010
1599 /* L3SQ general and high priority credit initialization. */
1600 # define IVB_L3SQCREG1_SQGHPCI_DEFAULT     0x00730000
1601 # define VLV_L3SQCREG1_SQGHPCI_DEFAULT     0x00d30000
1602 # define HSW_L3SQCREG1_SQGHPCI_DEFAULT     0x00610000
1603 # define GEN7_L3SQCREG1_CONV_DC_UC         (1 << 24)
1604 # define GEN7_L3SQCREG1_CONV_IS_UC         (1 << 25)
1605 # define GEN7_L3SQCREG1_CONV_C_UC          (1 << 26)
1606 # define GEN7_L3SQCREG1_CONV_T_UC          (1 << 27)
1607 
1608 #define GEN7_L3CNTLREG2                    0xb020
1609 # define GEN7_L3CNTLREG2_SLM_ENABLE        (1 << 0)
1610 # define GEN7_L3CNTLREG2_URB_ALLOC_SHIFT   1
1611 # define GEN7_L3CNTLREG2_URB_ALLOC_MASK    INTEL_MASK(6, 1)
1612 # define GEN7_L3CNTLREG2_URB_LOW_BW        (1 << 7)
1613 # define GEN7_L3CNTLREG2_ALL_ALLOC_SHIFT   8
1614 # define GEN7_L3CNTLREG2_ALL_ALLOC_MASK    INTEL_MASK(13, 8)
1615 # define GEN7_L3CNTLREG2_RO_ALLOC_SHIFT    14
1616 # define GEN7_L3CNTLREG2_RO_ALLOC_MASK     INTEL_MASK(19, 14)
1617 # define GEN7_L3CNTLREG2_RO_LOW_BW         (1 << 20)
1618 # define GEN7_L3CNTLREG2_DC_ALLOC_SHIFT    21
1619 # define GEN7_L3CNTLREG2_DC_ALLOC_MASK     INTEL_MASK(26, 21)
1620 # define GEN7_L3CNTLREG2_DC_LOW_BW         (1 << 27)
1621 
1622 #define GEN7_L3CNTLREG3                    0xb024
1623 # define GEN7_L3CNTLREG3_IS_ALLOC_SHIFT    1
1624 # define GEN7_L3CNTLREG3_IS_ALLOC_MASK     INTEL_MASK(6, 1)
1625 # define GEN7_L3CNTLREG3_IS_LOW_BW         (1 << 7)
1626 # define GEN7_L3CNTLREG3_C_ALLOC_SHIFT     8
1627 # define GEN7_L3CNTLREG3_C_ALLOC_MASK      INTEL_MASK(13, 8)
1628 # define GEN7_L3CNTLREG3_C_LOW_BW          (1 << 14)
1629 # define GEN7_L3CNTLREG3_T_ALLOC_SHIFT     15
1630 # define GEN7_L3CNTLREG3_T_ALLOC_MASK      INTEL_MASK(20, 15)
1631 # define GEN7_L3CNTLREG3_T_LOW_BW          (1 << 21)
1632 
1633 #define HSW_SCRATCH1                       0xb038
1634 #define HSW_SCRATCH1_L3_ATOMIC_DISABLE     (1 << 27)
1635 
1636 #define HSW_ROW_CHICKEN3                   0xe49c
1637 #define HSW_ROW_CHICKEN3_L3_ATOMIC_DISABLE (1 << 6)
1638 
1639 #define GEN8_L3CNTLREG                     0x7034
1640 # define GEN8_L3CNTLREG_SLM_ENABLE         (1 << 0)
1641 # define GEN8_L3CNTLREG_URB_ALLOC_SHIFT    1
1642 # define GEN8_L3CNTLREG_URB_ALLOC_MASK     INTEL_MASK(7, 1)
1643 # define GEN8_L3CNTLREG_RO_ALLOC_SHIFT     11
1644 # define GEN8_L3CNTLREG_RO_ALLOC_MASK      INTEL_MASK(17, 11)
1645 # define GEN8_L3CNTLREG_DC_ALLOC_SHIFT     18
1646 # define GEN8_L3CNTLREG_DC_ALLOC_MASK      INTEL_MASK(24, 18)
1647 # define GEN8_L3CNTLREG_ALL_ALLOC_SHIFT    25
1648 # define GEN8_L3CNTLREG_ALL_ALLOC_MASK     INTEL_MASK(31, 25)
1649 
1650 #define GEN10_CACHE_MODE_SS            0x0e420
1651 #define GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 4)
1652 
1653 #define INSTPM                             0x20c0
1654 # define INSTPM_CONSTANT_BUFFER_ADDRESS_OFFSET_DISABLE (1 << 6)
1655 
1656 #define CS_DEBUG_MODE2                     0x20d8 /* Gen9+ */
1657 # define CSDBG2_CONSTANT_BUFFER_ADDRESS_OFFSET_DISABLE (1 << 4)
1658 
1659 #define SLICE_COMMON_ECO_CHICKEN1          0x731c /* Gen9+ */
1660 # define GLK_SCEC_BARRIER_MODE_GPGPU       (0 << 7)
1661 # define GLK_SCEC_BARRIER_MODE_3D_HULL     (1 << 7)
1662 # define GLK_SCEC_BARRIER_MODE_MASK        REG_MASK(1 << 7)
1663 
1664 #endif
1665