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Searched refs:MI_PREDICATE_SRC0 (Results 1 – 6 of 6) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_compute.c54 OUT_BATCH(MI_PREDICATE_SRC0 + 4); in prepare_indirect_gpgpu_walker()
63 brw_load_register_mem(brw, MI_PREDICATE_SRC0, bo, indirect_offset + 0); in prepare_indirect_gpgpu_walker()
74 brw_load_register_mem(brw, MI_PREDICATE_SRC0, bo, indirect_offset + 4); in prepare_indirect_gpgpu_walker()
85 brw_load_register_mem(brw, MI_PREDICATE_SRC0, bo, indirect_offset + 8); in prepare_indirect_gpgpu_walker()
Dbrw_conditional_render.c69 brw_load_register_reg64(brw, HSW_CS_GPR(0), MI_PREDICATE_SRC0); in set_predicate_for_overflow_query()
90 brw_load_register_mem64(brw, MI_PREDICATE_SRC0, query->bo, 0 /* offset */); in set_predicate_for_occlusion_query()
Dhsw_queryobj.c392 brw_load_register_mem64(brw, MI_PREDICATE_SRC0, query_bo, in set_predicate()
Dbrw_draw.c981 brw_load_register_mem(brw, MI_PREDICATE_SRC0, in brw_draw_prims()
985 brw_load_register_imm32(brw, MI_PREDICATE_SRC0 + 4, 0); in brw_draw_prims()
Dbrw_defines.h1588 #define MI_PREDICATE_SRC0 0x2400 macro
/external/mesa3d/src/intel/vulkan/
DgenX_cmd_buffer.c406 #define MI_PREDICATE_SRC0 0x2400 macro
452 emit_lri(&cmd_buffer->batch, MI_PREDICATE_SRC0 , 0); in genX()
453 emit_lrm(&cmd_buffer->batch, MI_PREDICATE_SRC0 + 4, in genX()
2743 emit_lri(batch, MI_PREDICATE_SRC0 + 4, 0); in genX()
2748 emit_lrm(batch, MI_PREDICATE_SRC0, bo, bo_offset + 0); in genX()
2758 emit_lrm(batch, MI_PREDICATE_SRC0, bo, bo_offset + 4); in genX()
2768 emit_lrm(batch, MI_PREDICATE_SRC0, bo, bo_offset + 8); in genX()