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Searched refs:MI_PREDICATE_SRC1 (Results 1 – 6 of 6) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_conditional_render.c70 brw_load_register_imm64(brw, MI_PREDICATE_SRC1, 0ull); in set_predicate_for_overflow_query()
91 brw_load_register_mem64(brw, MI_PREDICATE_SRC1, query->bo, 8 /* offset */); in set_predicate_for_occlusion_query()
Dbrw_compute.c56 OUT_BATCH(MI_PREDICATE_SRC1 + 0); in prepare_indirect_gpgpu_walker()
58 OUT_BATCH(MI_PREDICATE_SRC1 + 4); in prepare_indirect_gpgpu_walker()
Dhsw_queryobj.c389 brw_load_register_imm64(brw, MI_PREDICATE_SRC1, 0ull); in set_predicate()
Dbrw_defines.h1589 #define MI_PREDICATE_SRC1 0x2408 macro
Dbrw_draw.c987 brw_load_register_imm64(brw, MI_PREDICATE_SRC1, prims[i].draw_id); in brw_draw_prims()
/external/mesa3d/src/intel/vulkan/
DgenX_cmd_buffer.c407 #define MI_PREDICATE_SRC1 0x2408 macro
450 emit_lri(&cmd_buffer->batch, MI_PREDICATE_SRC1 , 0); in genX()
451 emit_lri(&cmd_buffer->batch, MI_PREDICATE_SRC1 + 4, 0); in genX()
2744 emit_lri(batch, MI_PREDICATE_SRC1 + 0, 0); in genX()
2745 emit_lri(batch, MI_PREDICATE_SRC1 + 4, 0); in genX()