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Searched refs:MIb (Results 1 – 25 of 34) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DR600ControlFlowFinalizer.cpp353 MachineInstr *MIb = BuildMI(MBB, ClauseHead, MBB.findDebugLoc(ClauseHead), in MakeFetchClause() local
357 return ClauseFile(MIb, std::move(ClauseContent)); in MakeFetchClause()
572 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI), in runOnMachineFunction() local
577 Pair.second.insert(MIb); in runOnMachineFunction()
597 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI), in runOnMachineFunction() local
601 IfThenElseStack.push_back(MIb); in runOnMachineFunction()
602 LLVM_DEBUG(dbgs() << CfCount << ":"; MIb->dump();); in runOnMachineFunction()
611 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI), in runOnMachineFunction() local
615 LLVM_DEBUG(dbgs() << CfCount << ":"; MIb->dump();); in runOnMachineFunction()
616 IfThenElseStack.push_back(MIb); in runOnMachineFunction()
[all …]
DSIInstrInfo.cpp2119 MachineInstr &MIb) const { in checkInstOffsetsDoNotOverlap()
2124 getMemOpBaseRegImmOfs(MIb, BaseReg1, Offset1, &RI)) { in checkInstOffsetsDoNotOverlap()
2126 if (!MIa.hasOneMemOperand() || !MIb.hasOneMemOperand()) { in checkInstOffsetsDoNotOverlap()
2131 unsigned Width1 = (*MIb.memoperands_begin())->getSize(); in checkInstOffsetsDoNotOverlap()
2142 MachineInstr &MIb, in areMemAccessesTriviallyDisjoint() argument
2146 assert((MIb.mayLoad() || MIb.mayStore()) && in areMemAccessesTriviallyDisjoint()
2149 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects()) in areMemAccessesTriviallyDisjoint()
2153 if (MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
2156 if (AA && MIa.hasOneMemOperand() && MIb.hasOneMemOperand()) { in areMemAccessesTriviallyDisjoint()
2158 const MachineMemOperand *MMOb = *MIb.memoperands_begin(); in areMemAccessesTriviallyDisjoint()
[all …]
/external/llvm/lib/Target/AMDGPU/
DR600ControlFlowFinalizer.cpp337 MachineInstr *MIb = BuildMI(MBB, ClauseHead, MBB.findDebugLoc(ClauseHead), in MakeFetchClause() local
341 return ClauseFile(MIb, std::move(ClauseContent)); in MakeFetchClause()
557 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI), in runOnMachineFunction() local
562 Pair.second.insert(MIb); in runOnMachineFunction()
582 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI), in runOnMachineFunction() local
586 IfThenElseStack.push_back(MIb); in runOnMachineFunction()
587 DEBUG(dbgs() << CfCount << ":"; MIb->dump();); in runOnMachineFunction()
596 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI), in runOnMachineFunction() local
600 DEBUG(dbgs() << CfCount << ":"; MIb->dump();); in runOnMachineFunction()
601 IfThenElseStack.push_back(MIb); in runOnMachineFunction()
[all …]
DSIInstrInfo.cpp1342 MachineInstr &MIb) const { in checkInstOffsetsDoNotOverlap()
1347 getMemOpBaseRegImmOfs(MIb, BaseReg1, Offset1, &RI)) { in checkInstOffsetsDoNotOverlap()
1349 if (!MIa.hasOneMemOperand() || !MIb.hasOneMemOperand()) { in checkInstOffsetsDoNotOverlap()
1354 unsigned Width1 = (*MIb.memoperands_begin())->getSize(); in checkInstOffsetsDoNotOverlap()
1365 MachineInstr &MIb, in areMemAccessesTriviallyDisjoint() argument
1369 assert((MIb.mayLoad() || MIb.mayStore()) && in areMemAccessesTriviallyDisjoint()
1372 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects()) in areMemAccessesTriviallyDisjoint()
1376 if (MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
1385 if (isDS(MIb)) in areMemAccessesTriviallyDisjoint()
1386 return checkInstOffsetsDoNotOverlap(MIa, MIb); in areMemAccessesTriviallyDisjoint()
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DSIInstrInfo.h84 bool checkInstOffsetsDoNotOverlap(MachineInstr &MIa, MachineInstr &MIb) const;
167 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
/external/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCDuplexInfo.cpp573 MCInst const &MIb, bool ExtendedB, in isOrderedDuplexPair() argument
580 unsigned Opcode = MIb.getOpcode(); in isOrderedDuplexPair()
585 MIbG = HexagonMCInstrInfo::getDuplexCandidateGroup(MIb); in isOrderedDuplexPair()
594 MCInst SubInst1 = HexagonMCInstrInfo::deriveSubInst(MIb); in isOrderedDuplexPair()
608 if (MIb.getOpcode() == Hexagon::S2_allocframe) in isOrderedDuplexPair()
620 if (subInstWouldBeExtended(MIb) && !ExtendedB) in isOrderedDuplexPair()
626 if ((MIb.getNumOperands() > 1) && MIb.getOperand(1).isReg() && in isOrderedDuplexPair()
627 (MIb.getOperand(1).getReg() == Hexagon::R31)) in isOrderedDuplexPair()
629 if ((MIb.getNumOperands() > 0) && MIb.getOperand(0).isReg() && in isOrderedDuplexPair()
630 (MIb.getOperand(0).getReg() == Hexagon::R31)) in isOrderedDuplexPair()
[all …]
DHexagonMCCompound.cpp346 MCInst const &MIb, bool IsExtendedB) { in isOrderedCompoundPair() argument
348 unsigned MIbG = getCompoundCandidateGroup(MIb, IsExtendedB); in isOrderedCompoundPair()
356 (MIa.getOperand(0).getReg() == MIb.getOperand(0).getReg())); in isOrderedCompoundPair()
DHexagonMCInstrInfo.h201 bool isDuplexPair(MCInst const &MIa, MCInst const &MIb);
238 bool ExtendedA, MCInst const &MIb, bool ExtendedB,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCDuplexInfo.cpp575 MCInst const &MIb, bool ExtendedB, in isOrderedDuplexPair() argument
583 unsigned Opcode = MIb.getOpcode(); in isOrderedDuplexPair()
588 MIbG = HexagonMCInstrInfo::getDuplexCandidateGroup(MIb); in isOrderedDuplexPair()
597 MCInst SubInst1 = HexagonMCInstrInfo::deriveSubInst(MIb); in isOrderedDuplexPair()
611 if (MIb.getOpcode() == Hexagon::S2_allocframe) in isOrderedDuplexPair()
623 if (subInstWouldBeExtended(MIb) && !ExtendedB) in isOrderedDuplexPair()
629 if ((MIb.getNumOperands() > 1) && MIb.getOperand(1).isReg() && in isOrderedDuplexPair()
630 (MIb.getOperand(1).getReg() == Hexagon::R31)) in isOrderedDuplexPair()
632 if ((MIb.getNumOperands() > 0) && MIb.getOperand(0).isReg() && in isOrderedDuplexPair()
633 (MIb.getOperand(0).getReg() == Hexagon::R31)) in isOrderedDuplexPair()
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DHexagonMCCompound.cpp337 MCInst const &MIb, bool IsExtendedB) { in isOrderedCompoundPair() argument
339 unsigned MIbG = getCompoundCandidateGroup(MIb, IsExtendedB); in isOrderedCompoundPair()
347 (MIa.getOperand(0).getReg() == MIb.getOperand(0).getReg())); in isOrderedCompoundPair()
DHexagonMCInstrInfo.h225 bool isDuplexPair(MCInst const &MIa, MCInst const &MIb);
260 bool ExtendedA, MCInst const &MIb, bool ExtendedB,
/external/honggfuzz/examples/apache-httpd/corpus_http1/
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11 (>���{E���� �%�������9=�᪅^��C��MIb��U?""ߟ�>0����������������������������������������������������…
/external/honggfuzz/examples/apache-httpd/corpus_http2/
D9f77635d8c242affd50ef63913143b2b.000007be.honggfuzz.cov9 (>���{E���� �%�������9=�᪅^��C��MIb��U?""ߟ��9�5T]F����}3�A�lہ��l9s��x�Ƒ���-��L��O�tJ=�(�2…
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/external/llvm/lib/Target/Lanai/
DLanaiInstrInfo.cpp90 MachineInstr &MIb, in areMemAccessesTriviallyDisjoint() argument
93 assert(MIb.mayLoadOrStore() && "MIb must be a load or store."); in areMemAccessesTriviallyDisjoint()
95 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() || in areMemAccessesTriviallyDisjoint()
96 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
109 getMemOpBaseRegImmOfsWidth(MIb, BaseRegB, OffsetB, WidthB, TRI)) { in areMemAccessesTriviallyDisjoint()
DLanaiInstrInfo.h38 bool areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/
DLanaiInstrInfo.cpp90 MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis * /*AA*/) const { in areMemAccessesTriviallyDisjoint() argument
92 assert(MIb.mayLoadOrStore() && "MIb must be a load or store."); in areMemAccessesTriviallyDisjoint()
94 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() || in areMemAccessesTriviallyDisjoint()
95 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
108 getMemOpBaseRegImmOfsWidth(MIb, BaseRegB, OffsetB, WidthB, TRI)) { in areMemAccessesTriviallyDisjoint()
DLanaiInstrInfo.h39 bool areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.h269 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
302 bool isDuplexPair(const MachineInstr *MIa, const MachineInstr *MIb) const;
/external/llvm/include/llvm/Target/
DTargetInstrInfo.h1427 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
1431 assert((MIb.mayLoad() || MIb.mayStore()) &&
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.h299 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
365 bool isDuplexPair(const MachineInstr &MIa, const MachineInstr &MIb) const;
DHexagonInstrInfo.cpp1816 MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA) const { in areMemAccessesTriviallyDisjoint() argument
1817 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() || in areMemAccessesTriviallyDisjoint()
1818 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
1823 if (MIa.mayLoad() && !isMemOp(MIa) && MIb.mayLoad() && !isMemOp(MIb)) in areMemAccessesTriviallyDisjoint()
1836 if (!getBaseAndOffsetPosition(MIb, BasePosB, OffsetPosB)) in areMemAccessesTriviallyDisjoint()
1838 const MachineOperand &BaseB = MIb.getOperand(BasePosB); in areMemAccessesTriviallyDisjoint()
1847 unsigned SizeB = getMemAccessSize(MIb); in areMemAccessesTriviallyDisjoint()
1851 const MachineOperand &OffB = MIb.getOperand(OffsetPosB); in areMemAccessesTriviallyDisjoint()
1853 !MIb.getOperand(OffsetPosB).isImm()) in areMemAccessesTriviallyDisjoint()
1856 int OffsetB = isPostIncrement(MIb) ? 0 : OffB.getImm(); in areMemAccessesTriviallyDisjoint()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64LoadStoreOptimizer.cpp1019 static bool mayAlias(MachineInstr &MIa, MachineInstr &MIb, in mayAlias() argument
1022 if (!MIa.mayStore() && !MIb.mayStore()) in mayAlias()
1026 if (!MIa.mayLoadOrStore() && !MIb.mayLoadOrStore()) in mayAlias()
1029 return MIa.mayAlias(AA, MIb, /*UseTBAA*/false); in mayAlias()
1035 for (MachineInstr *MIb : MemInsns) in mayAlias()
1036 if (mayAlias(MIa, *MIb, AA)) in mayAlias()
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DTargetInstrInfo.h1527 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
1531 assert((MIb.mayLoad() || MIb.mayStore()) &&
/external/llvm/lib/Target/AArch64/
DAArch64LoadStoreOptimizer.cpp1075 static bool mayAlias(MachineInstr &MIa, MachineInstr &MIb, in mayAlias() argument
1078 if (!MIa.mayStore() && !MIb.mayStore()) in mayAlias()
1082 if (!MIa.mayLoadOrStore() && !MIb.mayLoadOrStore()) in mayAlias()
1085 return !TII->areMemAccessesTriviallyDisjoint(MIa, MIb); in mayAlias()
1091 for (MachineInstr *MIb : MemInsns) in mayAlias()
1092 if (mayAlias(MIa, *MIb, TII)) in mayAlias()
/external/llvm/lib/CodeGen/
DScheduleDAGInstrs.cpp564 MachineInstr *MIb) { in MIsNeedChainEdge() argument
568 assert ((MIa->mayStore() || MIb->mayStore()) && in MIsNeedChainEdge()
572 if (TII->areMemAccessesTriviallyDisjoint(*MIa, *MIb, AA)) in MIsNeedChainEdge()
580 if (!MIa->hasOneMemOperand() || !MIb->hasOneMemOperand()) in MIsNeedChainEdge()
584 MachineMemOperand *MMOb = *MIb->memoperands_begin(); in MIsNeedChainEdge()

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