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1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (C) 2016 Freescale Semiconductor, Inc.
4  */
5 
6 #ifndef _MX7ULP_REGS_H_
7 #define _MX7ULP_REGS_H_
8 
9 #include <linux/sizes.h>
10 
11 #define CAAM_SEC_SRAM_BASE      (0x26000000)
12 #define CAAM_SEC_SRAM_SIZE      (SZ_32K)
13 #define CAAM_SEC_SRAM_END       (CAAM_SEC_SRAM_BASE + CAAM_SEC_SRAM_SIZE - 1)
14 
15 #define OCRAM_0_BASE            (0x2F000000)
16 #define OCRAM_0_SIZE            (SZ_128K)
17 #define OCRAM_0_END             (OCRAM_0_BASE + OCRAM_0_SIZE - 1)
18 
19 #define OCRAM_1_BASE            (0x2F020000)
20 #define OCRAM_1_SIZE            (SZ_128K)
21 #define OCRAM_1_END             (OCRAM_1_BASE + OCRAM_1_SIZE - 1)
22 
23 #define TCML_BASE               (0x1FFD0000)
24 #define TCMU_BASE               (0x20000000)
25 
26 #define AIPS3_BASE			(0x40800000UL)
27 #define AIPS3_SLOT_SIZE			(SZ_64K)
28 #define AIPS2_BASE			(0x40000000UL)
29 #define AIPS2_SLOT_SIZE			(SZ_64K)
30 #define AIPS1_BASE			(0x41080000UL)
31 #define AIPS1_SLOT_SIZE			(SZ_4K)
32 #define AIPS0_BASE			(0x41000000UL)
33 #define AIPS0_SLOT_SIZE			(SZ_4K)
34 #define IOMUXC0_AIPS0_SLOT		(61)
35 #define WDG0_AIPS0_SLOT			(37)
36 #define WDG1_AIPS2_SLOT			(61)
37 #define WDG2_AIPS2_SLOT			(67)
38 #define WDG0_PCC0_SLOT			(37)
39 #define IOMUXC1_AIPS3_SLOT		(44)
40 #define CMC0_AIPS1_SLOT			(36)
41 #define CMC1_AIPS2_SLOT			(65)
42 #define SCG0_AIPS0_SLOT			(39)
43 #define PCC0_AIPS0_SLOT			(38)
44 #define PCC1_AIPS1_SLOT			(50)
45 #define PCC2_AIPS2_SLOT			(63)
46 #define PCC3_AIPS3_SLOT			(51)
47 #define SCG1_AIPS2_SLOT			(62)
48 #define SIM0_AIPS1_SLOT			(35)
49 #define SIM1_AIPS1_SLOT			(48)
50 #define USBOTG0_AIPS2_SLOT		(51)
51 #define USBOTG1_AIPS2_SLOT		(52)
52 #define USBPHY_AIPS2_SLOT		(53)
53 #define USDHC0_AIPS2_SLOT		(55)
54 #define USDHC1_AIPS2_SLOT		(56)
55 #define RGPIO2P0_AIPS0_SLOT		(15)
56 #define RGPIO2P1_AIPS2_SLOT		(15)
57 #define IOMUXC0_AIPS0_SLOT		(61)
58 #define OCOTP_CTRL_AIPS1_SLOT		(38)
59 #define OCOTP_CTRL_PCC1_SLOT		(38)
60 #define SIM1_PCC1_SLOT			(48)
61 #define MMDC0_AIPS3_SLOT		(43)
62 #define IOMUXC_DDR_AIPS3_SLOT		(45)
63 
64 #define LPI2C0_AIPS0_SLOT		(51)
65 #define LPI2C1_AIPS0_SLOT		(52)
66 #define LPI2C2_AIPS0_SLOT		(53)
67 #define LPI2C3_AIPS0_SLOT		(54)
68 #define LPI2C4_AIPS2_SLOT		(43)
69 #define LPI2C5_AIPS2_SLOT		(44)
70 #define LPI2C6_AIPS3_SLOT		(36)
71 #define LPI2C7_AIPS3_SLOT		(37)
72 
73 #define LPUART0_PCC0_SLOT		(58)
74 #define LPUART1_PCC0_SLOT		(59)
75 #define LPUART2_PCC1_SLOT		(43)
76 #define LPUART3_PCC1_SLOT		(44)
77 #define LPUART0_AIPS0_SLOT		(58)
78 #define LPUART1_AIPS0_SLOT		(59)
79 #define LPUART2_AIPS1_SLOT		(43)
80 #define LPUART3_AIPS1_SLOT		(44)
81 #define LPUART4_AIPS2_SLOT		(45)
82 #define LPUART5_AIPS2_SLOT		(46)
83 #define LPUART6_AIPS3_SLOT		(38)
84 #define LPUART7_AIPS3_SLOT		(39)
85 
86 #define CORE_B_ROM_SIZE			(SZ_32K + SZ_64K)
87 #define CORE_B_ROM_BASE			(0x00000000)
88 
89 #define ROMCP_ARB_BASE_ADDR		CORE_B_ROM_BASE
90 #define ROMCP_ARB_END_ADDR		CORE_B_ROM_SIZE
91 #define IRAM_BASE_ADDR			OCRAM_0_BASE
92 #define IRAM_SIZE			(SZ_128K + SZ_128K)
93 
94 #define IOMUXC_PCR_MUX_ALT0		(0<<8)
95 #define IOMUXC_PCR_MUX_ALT1		(1<<8)
96 #define IOMUXC_PCR_MUX_ALT2		(2<<8)
97 #define IOMUXC_PCR_MUX_ALT3		(3<<8)
98 #define IOMUXC_PCR_MUX_ALT4		(4<<8)
99 #define IOMUXC_PCR_MUX_ALT5		(5<<8)
100 #define IOMUXC_PCR_MUX_ALT6		(6<<8)
101 #define IOMUXC_PCR_MUX_ALT7		(7<<8)
102 #define IOMUXC_PCR_MUX_ALT8		(8<<8)
103 #define IOMUXC_PCR_MUX_ALT9		(9<<8)
104 #define IOMUXC_PCR_MUX_ALT10		(10<<8)
105 #define IOMUXC_PCR_MUX_ALT11		(11<<8)
106 #define IOMUXC_PCR_MUX_ALT12		(12<<8)
107 #define IOMUXC_PCR_MUX_ALT13		(13<<8)
108 #define IOMUXC_PCR_MUX_ALT14		(14<<8)
109 #define IOMUXC_PCR_MUX_ALT15		(15<<8)
110 
111 #define IOMUXC_PSMI_IMUX_ALT0		(0x0)
112 #define IOMUXC_PSMI_IMUX_ALT1		(0x1)
113 #define IOMUXC_PSMI_IMUX_ALT2		(0x2)
114 #define IOMUXC_PSMI_IMUX_ALT3		(0x3)
115 #define IOMUXC_PSMI_IMUX_ALT4		(0x4)
116 #define IOMUXC_PSMI_IMUX_ALT5		(0x5)
117 #define IOMUXC_PSMI_IMUX_ALT6		(0x6)
118 #define IOMUXC_PSMI_IMUX_ALT7		(0x7)
119 
120 
121 #define SIM_SOPT1_EN_SNVS_HARD_RST	(1<<8)
122 #define SIM_SOPT1_PMIC_STBY_REQ		(1<<2)
123 #define SIM_SOPT1_A7_SW_RESET		(1<<0)
124 
125 #define IOMUXC_PCR_MUX_ALT_SHIFT	(8)
126 #define IOMUXC_PCR_MUX_ALT_MASK		(0xF00)
127 #define IOMUXC_PSMI_IMUX_ALT_SHIFT	(0)
128 
129 #define IOMUXC0_RBASE	((AIPS0_BASE + (AIPS0_SLOT_SIZE * IOMUXC0_AIPS0_SLOT)))
130 #define IOMUXC1_RBASE	((AIPS3_BASE + (AIPS3_SLOT_SIZE * IOMUXC1_AIPS3_SLOT)))
131 #define WDG0_RBASE	((AIPS0_BASE + (AIPS0_SLOT_SIZE * WDG0_AIPS0_SLOT)))
132 #define WDG1_RBASE	((AIPS2_BASE + (AIPS2_SLOT_SIZE * WDG1_AIPS2_SLOT)))
133 #define WDG2_RBASE	((AIPS2_BASE + (AIPS2_SLOT_SIZE * WDG2_AIPS2_SLOT)))
134 #define SCG0_RBASE	((AIPS0_BASE + (AIPS0_SLOT_SIZE * SCG0_AIPS0_SLOT)))
135 #define SCG1_RBASE	((AIPS2_BASE + (AIPS2_SLOT_SIZE * SCG1_AIPS2_SLOT)))
136 #define PCC0_RBASE	((AIPS0_BASE + (AIPS0_SLOT_SIZE * PCC0_AIPS0_SLOT)))
137 #define PCC1_RBASE	((AIPS1_BASE + (AIPS1_SLOT_SIZE * PCC1_AIPS1_SLOT)))
138 #define PCC2_RBASE	((AIPS2_BASE + (AIPS2_SLOT_SIZE * PCC2_AIPS2_SLOT)))
139 #define PCC3_RBASE	((AIPS3_BASE + (AIPS3_SLOT_SIZE * PCC3_AIPS3_SLOT)))
140 #define IOMUXC0_RBASE	((AIPS0_BASE + (AIPS0_SLOT_SIZE * IOMUXC0_AIPS0_SLOT)))
141 #define PSMI0_RBASE	((IOMUXC0_RBASE + 0x100)) /* in iomuxc0 after pta and ptb */
142 #define CMC0_RBASE	((AIPS1_BASE + (AIPS1_SLOT_SIZE * CMC0_AIPS1_SLOT)))
143 #define CMC1_RBASE	((AIPS2_BASE + (AIPS2_SLOT_SIZE * CMC1_AIPS2_SLOT)))
144 #define OCOTP_BASE_ADDR	((AIPS1_BASE + (AIPS1_SLOT_SIZE * OCOTP_CTRL_AIPS1_SLOT)))
145 #define SIM0_RBASE	((AIPS1_BASE + (AIPS1_SLOT_SIZE * SIM0_AIPS1_SLOT)))
146 #define SIM1_RBASE	((AIPS1_BASE + (AIPS1_SLOT_SIZE * SIM1_AIPS1_SLOT)))
147 #define MMDC0_RBASE	((AIPS3_BASE + (AIPS3_SLOT_SIZE * MMDC0_AIPS3_SLOT)))
148 
149 #define USBOTG0_RBASE	((AIPS2_BASE + (AIPS2_SLOT_SIZE * USBOTG0_AIPS2_SLOT)))
150 #define USBOTG1_RBASE	((AIPS2_BASE + (AIPS2_SLOT_SIZE * USBOTG1_AIPS2_SLOT)))
151 #define USBPHY_RBASE	((AIPS2_BASE + (AIPS2_SLOT_SIZE * USBPHY_AIPS2_SLOT)))
152 #define USB_PHY0_BASE_ADDR	USBPHY_RBASE
153 #define USB_BASE_ADDR		USBOTG0_RBASE
154 
155 #define LPI2C1_BASE_ADDR	((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C0_AIPS0_SLOT)))
156 #define LPI2C2_BASE_ADDR	((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C1_AIPS0_SLOT)))
157 #define LPI2C3_BASE_ADDR	((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C2_AIPS0_SLOT)))
158 #define LPI2C4_BASE_ADDR	((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C3_AIPS0_SLOT)))
159 #define LPI2C5_BASE_ADDR	((AIPS2_BASE + (AIPS2_SLOT_SIZE * LPI2C4_AIPS2_SLOT)))
160 #define LPI2C6_BASE_ADDR	((AIPS2_BASE + (AIPS2_SLOT_SIZE * LPI2C5_AIPS2_SLOT)))
161 #define LPI2C7_BASE_ADDR	((AIPS3_BASE + (AIPS3_SLOT_SIZE * LPI2C6_AIPS3_SLOT)))
162 #define LPI2C8_BASE_ADDR	((AIPS3_BASE + (AIPS3_SLOT_SIZE * LPI2C7_AIPS3_SLOT)))
163 
164 #define LPUART0_RBASE	((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPUART0_AIPS0_SLOT)))
165 #define LPUART1_RBASE	((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPUART1_AIPS0_SLOT)))
166 #define LPUART2_RBASE	((AIPS1_BASE + (AIPS1_SLOT_SIZE * LPUART2_AIPS1_SLOT)))
167 #define LPUART3_RBASE	((AIPS1_BASE + (AIPS1_SLOT_SIZE * LPUART3_AIPS1_SLOT)))
168 #define LPUART4_RBASE	((AIPS2_BASE + (AIPS2_SLOT_SIZE * LPUART4_AIPS2_SLOT)))
169 #define LPUART5_RBASE	((AIPS2_BASE + (AIPS2_SLOT_SIZE * LPUART5_AIPS2_SLOT)))
170 #define LPUART6_RBASE	((AIPS3_BASE + (AIPS3_SLOT_SIZE * LPUART6_AIPS3_SLOT)))
171 #define LPUART7_RBASE	((AIPS3_BASE + (AIPS3_SLOT_SIZE * LPUART7_AIPS3_SLOT)))
172 
173 #define USDHC0_RBASE	((AIPS2_BASE + (AIPS2_SLOT_SIZE * USDHC0_AIPS2_SLOT)))
174 #define USDHC1_RBASE	((AIPS2_BASE + (AIPS2_SLOT_SIZE * USDHC1_AIPS2_SLOT)))
175 
176 #define RGPIO2P0_RBASE	((AIPS0_BASE + (AIPS0_SLOT_SIZE * RGPIO2P0_AIPS0_SLOT)))
177 #define RGPIO2P1_RBASE	((AIPS2_BASE + (AIPS2_SLOT_SIZE * RGPIO2P1_AIPS2_SLOT)))
178 
179 #define WDG0_PCC_REG	(PCC0_RBASE + (4 * WDG0_PCC0_SLOT))
180 #define WDG1_PCC_REG	(PCC2_RBASE + (4 * WDG1_PCC2_SLOT))
181 #define CMC0_SRS	(CMC0_RBASE  + 0x20)
182 #define CMC0_SSRS	(CMC0_RBASE  + 0x28)
183 #define CMC1_SRS	(CMC1_RBASE  + 0x20)
184 #define CMC1_SSRS	(CMC1_RBASE  + 0x28)
185 
186 #define IOMUXC0_PCR0	(IOMUXC0_RBASE + (4 * 0))
187 #define IOMUXC0_PCR1	(IOMUXC0_RBASE + (4 * 1))
188 #define IOMUXC0_PCR2	(IOMUXC0_RBASE + (4 * 2))
189 #define IOMUXC0_PCR3	(IOMUXC0_RBASE + (4 * 3))
190 #define IOMUXC0_PSMI62	(PSMI0_RBASE + (4 * 62))
191 #define IOMUXC0_PSMI63	(PSMI0_RBASE + (4 * 63))
192 #define IOMUXC0_PSMI64	(PSMI0_RBASE + (4 * 64))
193 
194 #define SCG_CSR		(SCG0_RBASE + 0x010)
195 #define SCG_RCCR	(SCG0_RBASE + 0x014)
196 #define SCG_VCCR	(SCG0_RBASE + 0x018)
197 #define SCG_HCCR	(SCG0_RBASE + 0x01c)
198 
199 #define LPUART0_PCC_REG	(PCC0_RBASE + (4 * LPUART0_PCC0_SLOT))
200 #define LPUART1_PCC_REG	(PCC0_RBASE + (4 * LPUART1_PCC0_SLOT))
201 #define LPUART2_PCC_REG	(PCC1_RBASE + (4 * LPUART2_PCC1_SLOT))
202 #define LPUART3_PCC_REG	(PCC1_RBASE + (4 * LPUART3_PCC1_SLOT))
203 #define LPUART4_PCC_REG	(PCC2_RBASE + (4 * LPUART4_PCC2_SLOT))
204 #define LPUART5_PCC_REG	(PCC2_RBASE + (4 * LPUART5_PCC2_SLOT))
205 #define LPUART6_PCC_REG	(PCC3_RBASE + (4 * LPUART6_PCC3_SLOT))
206 #define LPUART7_PCC_REG	(PCC3_RBASE + (4 * LPUART7_PCC3_SLOT))
207 
208 #define USDHC0_PCC_REG	(PCC2_RBASE + (4 * USDHC0_PCC2_SLOT))
209 #define USDHC1_PCC_REG	(PCC2_RBASE + (4 * USDHC1_PCC2_SLOT))
210 
211 #define SIM1_PCC_REG	(PCC1_RBASE + (4 * SIM1_PCC1_SLOT))
212 #define SCG1_PCC_REG	(PCC2_RBASE + (4 * SCG1_PCC2_SLOT))
213 
214 #define OCOTP_CTRL_PCC_REG	(PCC1_RBASE + (4 * OCOTP_CTRL_PCC1_SLOT))
215 
216 #define IOMUXC_DDR_RBASE	((AIPS3_BASE + (AIPS3_SLOT_SIZE * IOMUXC_DDR_AIPS3_SLOT)))
217 #define MMDC0_PCC_REG		(PCC3_RBASE + (4 * MMDC0_PCC3_SLOT))
218 
219 #define IOMUXC_DPCR_DDR_DQS0	((IOMUXC_DDR_RBASE + (4 * 32)))
220 #define IOMUXC_DPCR_DDR_DQS1	((IOMUXC_DDR_RBASE + (4 * 33)))
221 #define IOMUXC_DPCR_DDR_DQS2	((IOMUXC_DDR_RBASE + (4 * 34)))
222 #define IOMUXC_DPCR_DDR_DQS3	((IOMUXC_DDR_RBASE + (4 * 35)))
223 
224 
225 #define IOMUXC_DPCR_DDR_DQ0	((IOMUXC_DDR_RBASE + (4 * 0)))
226 #define IOMUXC_DPCR_DDR_DQ1	((IOMUXC_DDR_RBASE + (4 * 1)))
227 #define IOMUXC_DPCR_DDR_DQ2	((IOMUXC_DDR_RBASE + (4 * 2)))
228 #define IOMUXC_DPCR_DDR_DQ3	((IOMUXC_DDR_RBASE + (4 * 3)))
229 #define IOMUXC_DPCR_DDR_DQ4	((IOMUXC_DDR_RBASE + (4 * 4)))
230 #define IOMUXC_DPCR_DDR_DQ5	((IOMUXC_DDR_RBASE + (4 * 5)))
231 #define IOMUXC_DPCR_DDR_DQ6	((IOMUXC_DDR_RBASE + (4 * 6)))
232 #define IOMUXC_DPCR_DDR_DQ7	((IOMUXC_DDR_RBASE + (4 * 7)))
233 #define IOMUXC_DPCR_DDR_DQ8	((IOMUXC_DDR_RBASE + (4 * 8)))
234 #define IOMUXC_DPCR_DDR_DQ9	((IOMUXC_DDR_RBASE + (4 * 9)))
235 #define IOMUXC_DPCR_DDR_DQ10	((IOMUXC_DDR_RBASE + (4 * 10)))
236 #define IOMUXC_DPCR_DDR_DQ11	((IOMUXC_DDR_RBASE + (4 * 11)))
237 #define IOMUXC_DPCR_DDR_DQ12	((IOMUXC_DDR_RBASE + (4 * 12)))
238 #define IOMUXC_DPCR_DDR_DQ13	((IOMUXC_DDR_RBASE + (4 * 13)))
239 #define IOMUXC_DPCR_DDR_DQ14	((IOMUXC_DDR_RBASE + (4 * 14)))
240 #define IOMUXC_DPCR_DDR_DQ15	((IOMUXC_DDR_RBASE + (4 * 15)))
241 #define IOMUXC_DPCR_DDR_DQ16	((IOMUXC_DDR_RBASE + (4 * 16)))
242 #define IOMUXC_DPCR_DDR_DQ17	((IOMUXC_DDR_RBASE + (4 * 17)))
243 #define IOMUXC_DPCR_DDR_DQ18	((IOMUXC_DDR_RBASE + (4 * 18)))
244 #define IOMUXC_DPCR_DDR_DQ19	((IOMUXC_DDR_RBASE + (4 * 19)))
245 #define IOMUXC_DPCR_DDR_DQ20	((IOMUXC_DDR_RBASE + (4 * 20)))
246 #define IOMUXC_DPCR_DDR_DQ21	((IOMUXC_DDR_RBASE + (4 * 21)))
247 #define IOMUXC_DPCR_DDR_DQ22	((IOMUXC_DDR_RBASE + (4 * 22)))
248 #define IOMUXC_DPCR_DDR_DQ23	((IOMUXC_DDR_RBASE + (4 * 23)))
249 #define IOMUXC_DPCR_DDR_DQ24	((IOMUXC_DDR_RBASE + (4 * 24)))
250 #define IOMUXC_DPCR_DDR_DQ25	((IOMUXC_DDR_RBASE + (4 * 25)))
251 #define IOMUXC_DPCR_DDR_DQ26	((IOMUXC_DDR_RBASE + (4 * 26)))
252 #define IOMUXC_DPCR_DDR_DQ27	((IOMUXC_DDR_RBASE + (4 * 27)))
253 #define IOMUXC_DPCR_DDR_DQ28	((IOMUXC_DDR_RBASE + (4 * 28)))
254 #define IOMUXC_DPCR_DDR_DQ29	((IOMUXC_DDR_RBASE + (4 * 29)))
255 #define IOMUXC_DPCR_DDR_DQ30	((IOMUXC_DDR_RBASE + (4 * 30)))
256 #define IOMUXC_DPCR_DDR_DQ31	((IOMUXC_DDR_RBASE + (4 * 31)))
257 
258 /* Remap the rgpio2p registers addr to driver's addr */
259 #define RGPIO2P_GPIO1_BASE_ADDR	RGPIO2P0_RBASE
260 #define RGPIO2P_GPIO2_BASE_ADDR	(RGPIO2P0_RBASE + 0x40)
261 #define RGPIO2P_GPIO3_BASE_ADDR	(RGPIO2P1_RBASE)
262 #define RGPIO2P_GPIO4_BASE_ADDR	(RGPIO2P1_RBASE + 0x40)
263 #define RGPIO2P_GPIO5_BASE_ADDR	(RGPIO2P1_RBASE + 0x80)
264 #define RGPIO2P_GPIO6_BASE_ADDR	(RGPIO2P1_RBASE + 0xc0)
265 
266 /* MMDC registers addresses */
267 #define MMDC_MDCTL_OFFSET	(0x000)
268 #define MMDC_MDPDC_OFFSET	(0x004)
269 #define MMDC_MDOTC_OFFSET	(0x008)
270 #define MMDC_MDCFG0_OFFSET	(0x00C)
271 #define MMDC_MDCFG1_OFFSET	(0x010)
272 #define MMDC_MDCFG2_OFFSET	(0x014)
273 #define MMDC_MDMISC_OFFSET	(0x018)
274 #define MMDC_MDSCR_OFFSET	(0x01C)
275 #define MMDC_MDREF_OFFSET	(0x020)
276 #define MMDC_MDRWD_OFFSET	(0x02C)
277 #define MMDC_MDOR_OFFSET	(0x030)
278 #define MMDC_MDMRR_OFFSET	(0x034)
279 #define MMDC_MDCFG3LP_OFFSET	(0x038)
280 #define MMDC_MDMR4_OFFSET	(0x03C)
281 #define MMDC_MDASP_OFFSET	(0x040)
282 
283 #define MMDC_MAARCR_OFFSET	(0x400)
284 #define MMDC_MAPSR_OFFSET	(0x404)
285 #define MMDC_MAEXIDR0_OFFSET	(0x408)
286 #define MMDC_MAEXIDR1_OFFSET	(0x40C)
287 #define MMDC_MADPCR0_OFFSET	(0x410)
288 #define MMDC_MADPCR1_OFFSET	(0x414)
289 #define MMDC_MADPSR0_OFFSET	(0x418)
290 #define MMDC_MADPSR1_OFFSET	(0x41C)
291 #define MMDC_MADPSR2_OFFSET	(0x420)
292 #define MMDC_MADPSR3_OFFSET	(0x424)
293 #define MMDC_MADPSR4_OFFSET	(0x428)
294 #define MMDC_MADPSR5_OFFSET	(0x42C)
295 #define MMDC_MASBS0_OFFSET	(0x430)
296 #define MMDC_MASBS1_OFFSET	(0x434)
297 #define MMDC_MAGENP_OFFSET	(0x440)
298 
299 #define MMDC_MPZQHWCTRL_OFFSET	(0x800)
300 #define MMDC_MPZQSWCTRL_OFFSET	(0x804)
301 #define MMDC_MPWLGCR_OFFSET	(0x808)
302 #define MMDC_MPWLDECTRL0_OFFSET	(0x80C)
303 #define MMDC_MPWLDECTRL1_OFFSET	(0x810)
304 #define MMDC_MPWLDLST_OFFSET	(0x814)
305 #define MMDC_MPODTCTRL_OFFSET	(0x818)
306 #define MMDC_MPREDQBY0DL_OFFSET	(0x81C)
307 #define MMDC_MPREDQBY1DL_OFFSET	(0x820)
308 #define MMDC_MPREDQBY2DL_OFFSET	(0x824)
309 #define MMDC_MPREDQBY3DL_OFFSET	(0x828)
310 #define MMDC_MPWRDQBY0DL_OFFSET	(0x82C)
311 #define MMDC_MPWRDQBY1DL_OFFSET	(0x830)
312 #define MMDC_MPWRDQBY2DL_OFFSET	(0x834)
313 #define MMDC_MPWRDQBY3DL_OFFSET	(0x838)
314 #define MMDC_MPDGCTRL0_OFFSET	(0x83C)
315 #define MMDC_MPDGCTRL1_OFFSET	(0x840)
316 #define MMDC_MPDGDLST_OFFSET	(0x844)
317 #define MMDC_MPRDDLCTL_OFFSET	(0x848)
318 #define MMDC_MPRDDLST_OFFSET	(0x84C)
319 #define MMDC_MPWRDLCTL_OFFSET	(0x850)
320 #define MMDC_MPWRDLST_OFFSET	(0x854)
321 #define MMDC_MPSDCTRL_OFFSET	(0x858)
322 #define MMDC_MPZQLP2CTL_OFFSET	(0x85C)
323 #define MMDC_MPRDDLHWCTL_OFFSET	(0x860)
324 #define MMDC_MPWRDLHWCTL_OFFSET	(0x864)
325 #define MMDC_MPRDDLHWST0_OFFSET	(0x868)
326 #define MMDC_MPRDDLHWST1_OFFSET	(0x86C)
327 #define MMDC_MPWRDLHWST0_OFFSET	(0x870)
328 #define MMDC_MPWRDLHWST1_OFFSET	(0x874)
329 #define MMDC_MPWLHWERR_OFFSET	(0x878)
330 #define MMDC_MPDGHWST0_OFFSET	(0x87C)
331 #define MMDC_MPDGHWST1_OFFSET	(0x880)
332 #define MMDC_MPDGHWST2_OFFSET	(0x884)
333 #define MMDC_MPDGHWST3_OFFSET	(0x888)
334 #define MMDC_MPPDCMPR1_OFFSET	(0x88C)
335 #define MMDC_MPPDCMPR2_OFFSET	(0x890)
336 #define MMDC_MPSWDAR_OFFSET	(0x894)
337 #define MMDC_MPSWDRDR0_OFFSET	(0x898)
338 #define MMDC_MPSWDRDR1_OFFSET	(0x89C)
339 #define MMDC_MPSWDRDR2_OFFSET	(0x8A0)
340 #define MMDC_MPSWDRDR3_OFFSET	(0x8A4)
341 #define MMDC_MPSWDRDR4_OFFSET	(0x8A8)
342 #define MMDC_MPSWDRDR5_OFFSET	(0x8AC)
343 #define MMDC_MPSWDRDR6_OFFSET	(0x8B0)
344 #define MMDC_MPSWDRDR7_OFFSET	(0x8B4)
345 #define MMDC_MPMUR_OFFSET	(0x8B8)
346 #define MMDC_MPWRCADL_OFFSET	(0x8BC)
347 #define MMDC_MPDCCR_OFFSET	(0x8C0)
348 #define MMDC_MPBC_OFFSET	(0x8C4)
349 #define MMDC_MPSWDRAR_OFFSET	(0x8C8)
350 
351 /* First MMDC invalid IPS address */
352 #define MMDC_IPS_ILL_ADDR_START_OFFSET	(0x8CC)
353 #define MMDC_REGS_BASE			MMDC0_RBASE
354 
355 #define MMDC_MDCTL	((MMDC_REGS_BASE + MMDC_MDCTL_OFFSET))
356 #define MMDC_MDPDC	((MMDC_REGS_BASE + MMDC_MDPDC_OFFSET))
357 #define MMDC_MDOTC	((MMDC_REGS_BASE + MMDC_MDOTC_OFFSET))
358 #define MMDC_MDCFG0	((MMDC_REGS_BASE + MMDC_MDCFG0_OFFSET))
359 #define MMDC_MDCFG1	((MMDC_REGS_BASE + MMDC_MDCFG1_OFFSET))
360 #define MMDC_MDCFG2	((MMDC_REGS_BASE + MMDC_MDCFG2_OFFSET))
361 #define MMDC_MDMISC	((MMDC_REGS_BASE + MMDC_MDMISC_OFFSET))
362 #define MMDC_MDSCR	((MMDC_REGS_BASE + MMDC_MDSCR_OFFSET))
363 #define MMDC_MDREF	((MMDC_REGS_BASE + MMDC_MDREF_OFFSET))
364 #define MMDC_MDRWD	((MMDC_REGS_BASE + MMDC_MDRWD_OFFSET))
365 #define MMDC_MDOR	((MMDC_REGS_BASE + MMDC_MDOR_OFFSET))
366 #define MMDC_MDMRR	((MMDC_REGS_BASE + MMDC_MDMRR_OFFSET))
367 #define MMDC_MDCFG3LP	((MMDC_REGS_BASE + MMDC_MDCFG3LP_OFFSET))
368 #define MMDC_MDMR4	((MMDC_REGS_BASE + MMDC_MDMR4_OFFSET))
369 #define MMDC_MDASP	((MMDC_REGS_BASE + MMDC_MDASP_OFFSET))
370 
371 #define MMDC_MAARCR	((MMDC_REGS_BASE + MMDC_MAARCR_OFFSET))
372 #define MMDC_MAPSR	((MMDC_REGS_BASE + MMDC_MAPSR_OFFSET))
373 #define MMDC_MAEXIDR0	((MMDC_REGS_BASE + MMDC_MAEXIDR0_OFFSET))
374 #define MMDC_MAEXIDR1	((MMDC_REGS_BASE + MMDC_MAEXIDR1_OFFSET))
375 #define MMDC_MADPCR0	((MMDC_REGS_BASE + MMDC_MADPCR0_OFFSET))
376 #define MMDC_MADPCR1	((MMDC_REGS_BASE + MMDC_MADPCR1_OFFSET))
377 #define MMDC_MADPSR0	((MMDC_REGS_BASE + MMDC_MADPSR0_OFFSET))
378 #define MMDC_MADPSR1	((MMDC_REGS_BASE + MMDC_MADPSR1_OFFSET))
379 #define MMDC_MADPSR2	((MMDC_REGS_BASE + MMDC_MADPSR2_OFFSET))
380 #define MMDC_MADPSR3	((MMDC_REGS_BASE + MMDC_MADPSR3_OFFSET))
381 #define MMDC_MADPSR4	((MMDC_REGS_BASE + MMDC_MADPSR4_OFFSET))
382 #define MMDC_MADPSR5	((MMDC_REGS_BASE + MMDC_MADPSR5_OFFSET))
383 #define MMDC_MASBS0	((MMDC_REGS_BASE + MMDC_MASBS0_OFFSET))
384 #define MMDC_MASBS1	((MMDC_REGS_BASE + MMDC_MASBS1_OFFSET))
385 #define MMDC_MAGENP	((MMDC_REGS_BASE + MMDC_MAGENP_OFFSET))
386 
387 #define MMDC_MPZQHWCTRL		((MMDC_REGS_BASE + MMDC_MPZQHWCTRL_OFFSET))
388 #define MMDC_MPZQSWCTRL		((MMDC_REGS_BASE + MMDC_MPZQSWCTRL_OFFSET))
389 #define MMDC_MPWLGCR		((MMDC_REGS_BASE + MMDC_MPWLGCR_OFFSET))
390 #define MMDC_MPWLDECTRL0	((MMDC_REGS_BASE + MMDC_MPWLDECTRL0_OFFSET))
391 #define MMDC_MPWLDECTRL1	((MMDC_REGS_BASE + MMDC_MPWLDECTRL1_OFFSET))
392 #define MMDC_MPWLDLST		((MMDC_REGS_BASE + MMDC_MPWLDLST_OFFSET))
393 #define MMDC_MPODTCTRL		((MMDC_REGS_BASE + MMDC_MPODTCTRL_OFFSET))
394 #define MMDC_MPREDQBY0DL	((MMDC_REGS_BASE + MMDC_MPREDQBY0DL_OFFSET))
395 #define MMDC_MPREDQBY1DL	((MMDC_REGS_BASE + MMDC_MPREDQBY1DL_OFFSET))
396 #define MMDC_MPREDQBY2DL	((MMDC_REGS_BASE + MMDC_MPREDQBY2DL_OFFSET))
397 #define MMDC_MPREDQBY3DL	((MMDC_REGS_BASE + MMDC_MPREDQBY3DL_OFFSET))
398 #define MMDC_MPWRDQBY0DL	((MMDC_REGS_BASE + MMDC_MPWRDQBY0DL_OFFSET))
399 #define MMDC_MPWRDQBY1DL	((MMDC_REGS_BASE + MMDC_MPWRDQBY1DL_OFFSET))
400 #define MMDC_MPWRDQBY2DL	((MMDC_REGS_BASE + MMDC_MPWRDQBY2DL_OFFSET))
401 #define MMDC_MPWRDQBY3DL	((MMDC_REGS_BASE + MMDC_MPWRDQBY3DL_OFFSET))
402 #define MMDC_MPDGCTRL0		((MMDC_REGS_BASE + MMDC_MPDGCTRL0_OFFSET))
403 #define MMDC_MPDGCTRL1		((MMDC_REGS_BASE + MMDC_MPDGCTRL1_OFFSET))
404 #define MMDC_MPDGDLST		((MMDC_REGS_BASE + MMDC_MPDGDLST_OFFSET))
405 #define MMDC_MPRDDLCTL		((MMDC_REGS_BASE + MMDC_MPRDDLCTL_OFFSET))
406 #define MMDC_MPRDDLST		((MMDC_REGS_BASE + MMDC_MPRDDLST_OFFSET))
407 #define MMDC_MPWRDLCTL		((MMDC_REGS_BASE + MMDC_MPWRDLCTL_OFFSET))
408 #define MMDC_MPWRDLST		((MMDC_REGS_BASE + MMDC_MPWRDLST_OFFSET))
409 #define MMDC_MPSDCTRL		((MMDC_REGS_BASE + MMDC_MPSDCTRL_OFFSET))
410 #define MMDC_MPZQLP2CTL		((MMDC_REGS_BASE + MMDC_MPZQLP2CTL_OFFSET))
411 #define MMDC_MPRDDLHWCTL	((MMDC_REGS_BASE + MMDC_MPRDDLHWCTL_OFFSET))
412 #define MMDC_MPWRDLHWCTL	((MMDC_REGS_BASE + MMDC_MPWRDLHWCTL_OFFSET))
413 #define MMDC_MPRDDLHWST0	((MMDC_REGS_BASE + MMDC_MPRDDLHWST0_OFFSET))
414 #define MMDC_MPRDDLHWST1	((MMDC_REGS_BASE + MMDC_MPRDDLHWST1_OFFSET))
415 #define MMDC_MPWRDLHWST0	((MMDC_REGS_BASE + MMDC_MPWRDLHWST0_OFFSET))
416 #define MMDC_MPWRDLHWST1	((MMDC_REGS_BASE + MMDC_MPWRDLHWST1_OFFSET))
417 #define MMDC_MPWLHWERR		((MMDC_REGS_BASE + MMDC_MPWLHWERR_OFFSET))
418 #define MMDC_MPDGHWST0		((MMDC_REGS_BASE + MMDC_MPDGHWST0_OFFSET))
419 #define MMDC_MPDGHWST1		((MMDC_REGS_BASE + MMDC_MPDGHWST1_OFFSET))
420 #define MMDC_MPDGHWST2		((MMDC_REGS_BASE + MMDC_MPDGHWST2_OFFSET))
421 #define MMDC_MPDGHWST3		((MMDC_REGS_BASE + MMDC_MPDGHWST3_OFFSET))
422 #define MMDC_MPPDCMPR1		((MMDC_REGS_BASE + MMDC_MPPDCMPR1_OFFSET))
423 #define MMDC_MPPDCMPR2		((MMDC_REGS_BASE + MMDC_MPPDCMPR2_OFFSET))
424 #define MMDC_MPSWDAR		((MMDC_REGS_BASE + MMDC_MPSWDAR_OFFSET))
425 #define MMDC_MPSWDRDR0		((MMDC_REGS_BASE + MMDC_MPSWDRDR0_OFFSET))
426 #define MMDC_MPSWDRDR1		((MMDC_REGS_BASE + MMDC_MPSWDRDR1_OFFSET))
427 #define MMDC_MPSWDRDR2		((MMDC_REGS_BASE + MMDC_MPSWDRDR2_OFFSET))
428 #define MMDC_MPSWDRDR3		((MMDC_REGS_BASE + MMDC_MPSWDRDR3_OFFSET))
429 #define MMDC_MPSWDRDR4		((MMDC_REGS_BASE + MMDC_MPSWDRDR4_OFFSET))
430 #define MMDC_MPSWDRDR5		((MMDC_REGS_BASE + MMDC_MPSWDRDR5_OFFSET))
431 #define MMDC_MPSWDRDR6		((MMDC_REGS_BASE + MMDC_MPSWDRDR6_OFFSET))
432 #define MMDC_MPSWDRDR7		((MMDC_REGS_BASE + MMDC_MPSWDRDR7_OFFSET))
433 #define MMDC_MPMUR		((MMDC_REGS_BASE + MMDC_MPMUR_OFFSET))
434 #define MMDC_MPWRCADL		((MMDC_REGS_BASE + MMDC_MPWRCADL_OFFSET))
435 #define MMDC_MPDCCR		((MMDC_REGS_BASE + MMDC_MPDCCR_OFFSET))
436 #define MMDC_MPBC		((MMDC_REGS_BASE + MMDC_MPBC_OFFSET))
437 #define MMDC_MPSWDRAR		((MMDC_REGS_BASE + MMDC_MPSWDRAR_OFFSET))
438 
439 /* MMDC registers bit defines */
440 #define MMDC_MDCTL_SDE_0		(31)
441 #define MMDC_MDCTL_SDE_1		(30)
442 #define MMDC_MDCTL_ROW			(24)
443 #define MMDC_MDCTL_COL			(20)
444 #define MMDC_MDCTL_BL			(19)
445 #define MMDC_MDCTL_DSIZ			(16)
446 
447 /* MDMISC */
448 #define MMDC_MDMISC_CS0_RDY		(31)
449 #define MMDC_MDMISC_CS1_RDY		(30)
450 #define MMDC_MDMISC_CK1_DEL		(22)
451 #define MMDC_MDMISC_CK1_GATING		(21)
452 #define MMDC_MDMISC_CALIB_PER_CS	(20)
453 #define MMDC_MDMISC_ADDR_MIRROR		(19)
454 #define MMDC_MDMISC_LHD			(18)
455 #define MMDC_MDMISC_WALAT		(16)
456 #define MMDC_MDMISC_BI			(12)
457 #define MMDC_MDMISC_LPDDR2_S		(11)
458 #define MMDC_MDMISC_MIF3_MODE		(9)
459 #define MMDC_MDMISC_RALAT		(6)
460 #define MMDC_MDMISC_DDR_4_BANK		(5)
461 #define MMDC_MDMISC_DDR_TYPE		(3)
462 #define MMDC_MDMISC_RST			(1)
463 
464 /* MPWLGCR */
465 #define MMDC_MPWLGCR_WL_HW_ERR		(8)
466 
467 /* MDSCR */
468 #define MMDC_MDSCR_CMD_ADDR_MSB		(24)
469 #define MMDC_MDSCR_MR_OP		(24)
470 #define MMDC_MDSCR_CMD_ADDR_LSB		(16)
471 #define MMDC_MDSCR_MR_ADDR		(16)
472 #define MMDC_MDSCR_CON_REQ		(15)
473 #define MMDC_MDSCR_CON_ACK		(14)
474 #define MMDC_MDSCR_MRR_READ_DATA_VALID	(10)
475 #define MMDC_MDSCR_WL_EN		(9)
476 #define MMDC_MDSCR_CMD			(4)
477 #define MMDC_MDSCR_CMD_CS		(3)
478 #define MMDC_MDSCR_CMD_BA		(0)
479 
480 /* MPZQHWCTRL */
481 #define MMDC_MPZQHWCTRL_ZQ_HW_FOR	(16)
482 #define MMDC_MPZQHWCTRL_ZQ_MODE		(0)
483 
484 /* MPZQSWCTRL */
485 #define MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP	(16)
486 #define MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL	(13)
487 #define MMDC_MPZQSWCTRL_ZQ_SW_PD	(12)
488 #define MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL	(7)
489 #define MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL	(2)
490 #define MMDC_MPZQSWCTRL_ZQ_SW_RES	(1)
491 #define MMDC_MPZQSWCTRL_ZQ_SW_FOR	(0)
492 
493 /* MPDGCTRL0 */
494 #define MMDC_MPDGCTRL0_RST_RD_FIFO	(31)
495 #define MMDC_MPDGCTRL0_DG_CMP_CYC	(30)
496 #define MMDC_MPDGCTRL0_DG_DIS		(29)
497 #define MMDC_MPDGCTRL0_HW_DG_EN		(28)
498 #define MMDC_MPDGCTRL0_HW_DG_ERR	(12)
499 
500 /* MPRDDLHWCTL */
501 #define MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC	(5)
502 #define MMDC_MPRDDLHWCTL_HW_RD_DL_EN		(4)
503 #define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR		(0)
504 
505 /* MPWRDLHWCTL */
506 #define MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC	(5)
507 #define MMDC_MPWRDLHWCTL_HW_WR_DL_EN		(4)
508 #define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR		(0)
509 
510 /* MPSWDAR */
511 #define MMDC_MPSWDAR_TEST_DUMMY_EN	(6)
512 #define MMDC_MPSWDAR_SW_DUM_CMP3	(5)
513 #define MMDC_MPSWDAR_SW_DUM_CMP2	(4)
514 #define MMDC_MPSWDAR_SW_DUM_CMP1	(3)
515 #define MMDC_MPSWDAR_SW_DUM_CMP0	(2)
516 #define MMDC_MPSWDAR_SW_DUMMY_RD	(1)
517 #define MMDC_MPSWDAR_SW_DUMMY_WR	(0)
518 
519 /* MADPCR0 */
520 #define MMDC_MADPCR0_SBS		(9)
521 #define MMDC_MADPCR0_SBS_EN		(8)
522 
523 /* MASBS1 */
524 #define MMDC_MASBS1_SBS_VLD		(0)
525 #define MMDC_MASBS1_SBS_TYPE		(1)
526 
527 /* MDREF */
528 #define MMDC_MDREF_REF_CNT		(16)
529 #define MMDC_MDREF_REF_SEL		(14)
530 #define MMDC_MDREF_REFR			(11)
531 #define MMDC_MDREF_START_REF		(0)
532 
533 /* MPWLGCR */
534 #define MMDC_MPWLGCR_HW_WL_EN		(0)
535 
536 /* MPBC */
537 #define MMDC_MPBC_BIST_DM_LP_EN		(0)
538 #define MMDC_MPBC_BIST_CA0_LP_EN	(1)
539 #define MMDC_MPBC_BIST_DQ0_LP_EN	(3)
540 #define MMDC_MPBC_BIST_DQ1_LP_EN	(4)
541 #define MMDC_MPBC_BIST_DQ2_LP_EN	(5)
542 #define MMDC_MPBC_BIST_DQ3_LP_EN	(6)
543 
544 /* MPMUR */
545 #define MMDC_MPMUR_FRC_MSR		(11)
546 
547 /* MPODTCTRL */
548 #define MMDC_MPODTCTRL_ODT_RD_ACT_EN	(3)
549 #define MMDC_MPODTCTRL_ODT_RD_PAS_EN	(2)
550 #define MMDC_MPODTCTRL_ODT_WR_ACT_EN	(1)
551 #define MMDC_MPODTCTRL_ODT_WR_PAS_EN	(0)
552 
553 /* MAPSR */
554 #define MMDC_MAPSR_DVACK		(25)
555 #define MMDC_MAPSR_LPACK		(24)
556 #define MMDC_MAPSR_DVFS			(21)
557 #define MMDC_MAPSR_LPMD			(20)
558 
559 /* MAARCR */
560 #define MMDC_MAARCR_ARCR_EXC_ERR_EN	(28)
561 
562 /* MPZQLP2CTL */
563 #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS	(24)
564 #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL	(16)
565 #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT	(0)
566 
567 /* MDCFG3LP */
568 #define MMDC_MDCFG3LP_tRC_LP		(16)
569 #define MMDC_MDCFG3LP_tRCD_LP		(8)
570 #define MMDC_MDCFG3LP_tRPpb_LP		(4)
571 #define MMDC_MDCFG3LP_tRPab_LP		(0)
572 
573 /* MDOR */
574 #define MMDC_MDOR_tXPR			(16)
575 #define MMDC_MDOR_SDE_to_RST		(8)
576 #define MMDC_MDOR_RST_to_CKE		(0)
577 
578 /* MDCFG0 */
579 #define MMDC_MDCFG0_tRFC		(24)
580 #define MMDC_MDCFG0_tXS			(16)
581 #define MMDC_MDCFG0_tXP			(13)
582 #define MMDC_MDCFG0_tXPDLL		(9)
583 #define MMDC_MDCFG0_tFAW		(4)
584 #define MMDC_MDCFG0_tCL			(0)
585 
586 /* MDCFG1 */
587 #define MMDC_MDCFG1_tRCD		(29)
588 #define MMDC_MDCFG1_tRP			(26)
589 #define MMDC_MDCFG1_tRC			(21)
590 #define MMDC_MDCFG1_tRAS		(16)
591 #define MMDC_MDCFG1_tRPA		(15)
592 #define MMDC_MDCFG1_tWR			(9)
593 #define MMDC_MDCFG1_tMRD		(5)
594 #define MMDC_MDCFG1_tCWL		(0)
595 
596 /* MDCFG2 */
597 #define MMDC_MDCFG2_tDLLK		(16)
598 #define MMDC_MDCFG2_tRTP		(6)
599 #define MMDC_MDCFG2_tWTR		(3)
600 #define MMDC_MDCFG2_tRRD		(0)
601 
602 /* MDRWD */
603 #define MMDC_MDRWD_tDAI			(16)
604 #define MMDC_MDRWD_RTW_SAME		(12)
605 #define MMDC_MDRWD_WTR_DIFF		(9)
606 #define MMDC_MDRWD_WTW_DIFF		(6)
607 #define MMDC_MDRWD_RTW_DIFF		(3)
608 #define MMDC_MDRWD_RTR_DIFF		(0)
609 
610 /* MDPDC */
611 #define MMDC_MDPDC_PRCT_1		(28)
612 #define MMDC_MDPDC_PRCT_0		(24)
613 #define MMDC_MDPDC_tCKE			(16)
614 #define MMDC_MDPDC_PWDT_1		(12)
615 #define MMDC_MDPDC_PWDT_0		(8)
616 #define MMDC_MDPDC_SLOW_PD		(7)
617 #define MMDC_MDPDC_BOTH_CS_PD		(6)
618 #define MMDC_MDPDC_tCKSRX		(3)
619 #define MMDC_MDPDC_tCKSRE		(0)
620 
621 /* MDASP */
622 #define MMDC_MDASP_CS0_END		(0)
623 
624 /* MAEXIDR0 */
625 #define MMDC_MAEXIDR0_EXC_ID_MONITOR1	(16)
626 #define MMDC_MAEXIDR0_EXC_ID_MONITOR0	(0)
627 
628 /* MAEXIDR1 */
629 #define MMDC_MAEXIDR1_EXC_ID_MONITOR3	(16)
630 #define MMDC_MAEXIDR1_EXC_ID_MONITOR2	(0)
631 
632 /* MPWRDLCTL */
633 #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3	(24)
634 #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2	(16)
635 #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1	(8)
636 #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0	(0)
637 
638 /* MPRDDLCTL */
639 #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3	(24)
640 #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2	(16)
641 #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1	(8)
642 #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0	(0)
643 
644 /* MPWRDQBY0DL */
645 #define MMDC_MPWRDQBY0DL_WR_DM0_DEL	(30)
646 #define MMDC_MPWRDQBY0DL_WR_DQ7_DEL	(28)
647 #define MMDC_MPWRDQBY0DL_WR_DQ6_DEL	(24)
648 #define MMDC_MPWRDQBY0DL_WR_DQ5_DEL	(20)
649 #define MMDC_MPWRDQBY0DL_WR_DQ4_DEL	(16)
650 #define MMDC_MPWRDQBY0DL_WR_DQ3_DEL	(12)
651 #define MMDC_MPWRDQBY0DL_WR_DQ2_DEL	(8)
652 #define MMDC_MPWRDQBY0DL_WR_DQ1_DEL	(4)
653 #define MMDC_MPWRDQBY0DL_WR_DQ0_DEL	(0)
654 
655 /* MPWRDQBY1DL */
656 #define MMDC_MPWRDQBY1DL_WR_DM1_DEL	(30)
657 #define MMDC_MPWRDQBY1DL_WR_DQ15_DEL	(28)
658 #define MMDC_MPWRDQBY1DL_WR_DQ14_DEL	(24)
659 #define MMDC_MPWRDQBY1DL_WR_DQ13_DEL	(20)
660 #define MMDC_MPWRDQBY1DL_WR_DQ12_DEL	(16)
661 #define MMDC_MPWRDQBY1DL_WR_DQ11_DEL	(12)
662 #define MMDC_MPWRDQBY1DL_WR_DQ10_DEL	(8)
663 #define MMDC_MPWRDQBY1DL_WR_DQ9_DEL	(4)
664 #define MMDC_MPWRDQBY1DL_WR_DQ8_DEL	(0)
665 
666 /* MPWRDQBY2DL */
667 #define MMDC_MPWRDQBY2DL_WR_DM2_DEL	(30)
668 #define MMDC_MPWRDQBY2DL_WR_DQ23_DEL	(28)
669 #define MMDC_MPWRDQBY2DL_WR_DQ22_DEL	(24)
670 #define MMDC_MPWRDQBY2DL_WR_DQ21_DEL	(20)
671 #define MMDC_MPWRDQBY2DL_WR_DQ20_DEL	(16)
672 #define MMDC_MPWRDQBY2DL_WR_DQ19_DEL	(12)
673 #define MMDC_MPWRDQBY2DL_WR_DQ18_DEL	(8)
674 #define MMDC_MPWRDQBY2DL_WR_DQ17_DEL	(4)
675 #define MMDC_MPWRDQBY2DL_WR_DQ16_DEL	(0)
676 
677 /* MPWRDQBY3DL */
678 #define MMDC_MPWRDQBY3DL_WR_DM3_DEL	(30)
679 #define MMDC_MPWRDQBY3DL_WR_DQ31_DEL	(28)
680 #define MMDC_MPWRDQBY3DL_WR_DQ30_DEL	(24)
681 #define MMDC_MPWRDQBY3DL_WR_DQ29_DEL	(20)
682 #define MMDC_MPWRDQBY3DL_WR_DQ28_DEL	(16)
683 #define MMDC_MPWRDQBY3DL_WR_DQ27_DEL	(12)
684 #define MMDC_MPWRDQBY3DL_WR_DQ26_DEL	(8)
685 #define MMDC_MPWRDQBY3DL_WR_DQ25_DEL	(4)
686 #define MMDC_MPWRDQBY3DL_WR_DQ24_DEL	(0)
687 
688 /* Fields masks */
689 #define MMDC_MDCTL_SDE_0_MASK	((0x1 << MMDC_MDCTL_SDE_0))
690 #define MMDC_MDCTL_SDE_1_MASK	((0x1 << MMDC_MDCTL_SDE_1))
691 #define MMDC_MDCTL_BL_MASK	((0x1 << MMDC_MDCTL_BL))
692 #define MMDC_MDCTL_ROW_MASK	((0x7 << MMDC_MDCTL_ROW))
693 #define MMDC_MDCTL_COL_MASK	((0x7 << MMDC_MDCTL_COL))
694 #define MMDC_MDCTL_DSIZ_MASK	((0x3 << MMDC_MDCTL_DSIZ))
695 
696 /* MDMISC */
697 #define MMDC_MDMISC_CS0_RDY_MASK	((0x1 << MMDC_MDMISC_CS0_RDY))
698 #define MMDC_MDMISC_CS1_RDY_MASK	((0x1 << MMDC_MDMISC_CS1_RDY))
699 #define MMDC_MDMISC_CK1_DEL_MASK	((0x3 << MMDC_MDMISC_CK1_DEL))
700 #define MMDC_MDMISC_CK1_GATING_MASK	((0x1 << MMDC_MDMISC_CK1_GATING))
701 #define MMDC_MDMISC_CALIB_PER_CS_MASK	((0x1 << MMDC_MDMISC_CALIB_PER_CS))
702 #define MMDC_MDMISC_ADDR_MIRROR_MASK	((0x1 << MMDC_MDMISC_ADDR_MIRROR))
703 #define MMDC_MDMISC_LHD_MASK		((0x1 << MMDC_MDMISC_LHD))
704 #define MMDC_MDMISC_WALAT_MASK		((0x3 << MMDC_MDMISC_WALAT))
705 #define MMDC_MDMISC_BI_MASK		((0x1 << MMDC_MDMISC_BI))
706 #define MMDC_MDMISC_LPDDR2_S_MASK	((0x1 << MMDC_MDMISC_LPDDR2_S))
707 #define MMDC_MDMISC_MIF3_MODE_MASK	((0x3 << MMDC_MDMISC_MIF3_MODE))
708 #define MMDC_MDMISC_RALAT_MASK		((0x7 << MMDC_MDMISC_RALAT))
709 #define MMDC_MDMISC_DDR_4_BANK_MASK	((0x1 << MMDC_MDMISC_DDR_4_BANK))
710 #define MMDC_MDMISC_DDR_TYPE_MASK	((0x3 << MMDC_MDMISC_DDR_TYPE))
711 #define MMDC_MDMISC_RST_MASK		((0x1 << MMDC_MDMISC_RST))
712 
713 /* MPWLGCR */
714 #define MMDC_MPWLGCR_WL_HW_ERR_MASK	((0xf << MMDC_MPWLGCR_WL_HW_ERR))
715 
716 /* MDSCR */
717 #define MMDC_MDSCR_CMD_ADDR_MSB_MASK	((0xff << MMDC_MDSCR_CMD_ADDR_MSB))
718 #define MMDC_MDSCR_MR_OP_MASK		((0xff << MMDC_MDSCR_MR_OP))
719 #define MMDC_MDSCR_CMD_ADDR_LSB_MASK	((0xff << MMDC_MDSCR_CMD_ADDR_LSB))
720 #define MMDC_MDSCR_MR_ADDR_MASK		((0xff << MMDC_MDSCR_MR_ADDR))
721 #define MMDC_MDSCR_CON_REQ_MASK		((0x1  << MMDC_MDSCR_CON_REQ))
722 #define MMDC_MDSCR_CON_ACK_MASK		((0x1  << MMDC_MDSCR_CON_ACK))
723 #define MMDC_MDSCR_MRR_READ_DATA_VALID_MASK	((0x1  << MMDC_MDSCR_MRR_READ_DATA_VALID))
724 #define MMDC_MDSCR_WL_EN_MASK		((0x1  << MMDC_MDSCR_WL_EN))
725 #define MMDC_MDSCR_CMD_MASK		((0x7  << MMDC_MDSCR_CMD))
726 #define MMDC_MDSCR_CMD_CS_MASK		((0x1  << MMDC_MDSCR_CMD_CS))
727 #define MMDC_MDSCR_CMD_BA_MASK		((0x7  << MMDC_MDSCR_CMD_BA))
728 
729 /* MPZQHWCTRL */
730 #define MMDC_MPZQHWCTRL_ZQ_HW_FOR_MASK	((0x1 << MMDC_MPZQHWCTRL_ZQ_HW_FOR))
731 #define MMDC_MPZQHWCTRL_ZQ_MODE_MASK	((0x3 << MMDC_MPZQHWCTRL_ZQ_MODE))
732 
733 /* MPZQSWCTRL */
734 #define MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP_MASK	((0x3  << MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP))
735 #define MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL_MASK	((0x1  << MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL))
736 #define MMDC_MPZQSWCTRL_ZQ_SW_PD_MASK		((0x1  << MMDC_MPZQSWCTRL_ZQ_SW_PD))
737 #define MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_MASK	((0x1f << MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL))
738 #define MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL_MASK	((0x1f << MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL))
739 #define MMDC_MPZQSWCTRL_ZQ_SW_RES_MASK		((0x1  << MMDC_MPZQSWCTRL_ZQ_SW_RES))
740 #define MMDC_MPZQSWCTRL_ZQ_SW_FOR_MASK		((0x1  << MMDC_MPZQSWCTRL_ZQ_SW_FOR))
741 
742 /* MPDGCTRL0 */
743 #define MMDC_MPDGCTRL0_RST_RD_FIFO_MASK		((0x1 << MMDC_MPDGCTRL0_RST_RD_FIFO))
744 #define MMDC_MPDGCTRL0_DG_CMP_CYC_MASK		((0x1 << MMDC_MPDGCTRL0_DG_CMP_CYC))
745 #define MMDC_MPDGCTRL0_DG_DIS_MASK		((0x1 << MMDC_MPDGCTRL0_DG_DIS))
746 #define MMDC_MPDGCTRL0_HW_DG_EN_MASK		((0x1 << MMDC_MPDGCTRL0_HW_DG_EN))
747 #define MMDC_MPDGCTRL0_HW_DG_ERR_MASK		((0x1 << MMDC_MPDGCTRL0_HW_DG_ERR))
748 
749 /* MPRDDLHWCTL */
750 #define MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC_MASK	((0x1 << MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC))
751 #define MMDC_MPRDDLHWCTL_HW_RD_DL_EN_MASK	((0x1 << MMDC_MPRDDLHWCTL_HW_RD_DL_EN))
752 #define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR_MASK	((0xf << MMDC_MPRDDLHWCTL_HW_RD_DL_ERR))
753 
754 /* MPWRDLHWCTL */
755 #define MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC_MASK	((0x1 << MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC))
756 #define MMDC_MPWRDLHWCTL_HW_WR_DL_EN_MASK	((0x1 << MMDC_MPWRDLHWCTL_HW_WR_DL_EN))
757 #define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR_MASK	((0xf << MMDC_MPWRDLHWCTL_HW_WR_DL_ERR))
758 
759 /* MPSWDAR */
760 #define MMDC_MPSWDAR_TEST_DUMMY_EN_MASK	((0x1 << MMDC_MPSWDAR_TEST_DUMMY_EN))
761 #define MMDC_MPSWDAR_SW_DUM_CMP3_MASK	((0x1 << MMDC_MPSWDAR_SW_DUM_CMP3))
762 #define MMDC_MPSWDAR_SW_DUM_CMP2_MASK	((0x1 << MMDC_MPSWDAR_SW_DUM_CMP2))
763 #define MMDC_MPSWDAR_SW_DUM_CMP1_MASK	((0x1 << MMDC_MPSWDAR_SW_DUM_CMP1))
764 #define MMDC_MPSWDAR_SW_DUM_CMP0_MASK	((0x1 << MMDC_MPSWDAR_SW_DUM_CMP0))
765 #define MMDC_MPSWDAR_SW_DUMMY_RD_MASK	((0x1 << MMDC_MPSWDAR_SW_DUMMY_RD))
766 #define MMDC_MPSWDAR_SW_DUMMY_WR_MASK	((0x1 << MMDC_MPSWDAR_SW_DUMMY_WR))
767 
768 /* MADPCR0 */
769 #define MMDC_MADPCR0_SBS_MASK		((0x1 << MMDC_MADPCR0_SBS))
770 #define MMDC_MADPCR0_SBS_EN_MASK	((0x1 << MMDC_MADPCR0_SBS_EN))
771 
772 /* MASBS1 */
773 #define MMDC_MASBS1_SBS_VLD_MASK	((0x1 << MMDC_MASBS1_SBS_VLD))
774 #define MMDC_MASBS1_SBS_TYPE_MASK	((0x1 << MMDC_MASBS1_SBS_TYPE))
775 
776 /* MDREF */
777 #define MMDC_MDREF_REF_CNT_MASK		((0xffff << MMDC_MDREF_REF_CNT))
778 #define MMDC_MDREF_REF_SEL_MASK		((0x3    << MMDC_MDREF_REF_SEL))
779 #define MMDC_MDREF_REFR_MASK		((0x7    << MMDC_MDREF_REFR))
780 #define MMDC_MDREF_START_REF_MASK	((0x1    << MMDC_MDREF_START_REF))
781 
782 /* MPWLGCR */
783 #define MMDC_MPWLGCR_HW_WL_EN_MASK	((0x1 << MMDC_MPWLGCR_HW_WL_EN))
784 
785 /* MPBC */
786 #define MMDC_MPBC_BIST_DM_LP_EN_MASK	((0x1 << MMDC_MPBC_BIST_DM_LP_EN))
787 #define MMDC_MPBC_BIST_CA0_LP_EN_MASK	((0x1 << MMDC_MPBC_BIST_CA0_LP_EN))
788 #define MMDC_MPBC_BIST_DQ0_LP_EN_MASK	((0x1 << MMDC_MPBC_BIST_DQ0_LP_EN))
789 #define MMDC_MPBC_BIST_DQ1_LP_EN_MASK	((0x1 << MMDC_MPBC_BIST_DQ1_LP_EN))
790 #define MMDC_MPBC_BIST_DQ2_LP_EN_MASK	((0x1 << MMDC_MPBC_BIST_DQ2_LP_EN))
791 #define MMDC_MPBC_BIST_DQ3_LP_EN_MASK	((0x1 << MMDC_MPBC_BIST_DQ3_LP_EN))
792 #define MMDC_MPBC_BIST_DQ_LP_EN_MASK	((0xf << MMDC_MPBC_BIST_DQ0_LP_EN))
793 
794 /* MPMUR */
795 #define MMDC_MPMUR_FRC_MSR_MASK		((0x1 << MMDC_MPMUR_FRC_MSR))
796 
797 /* MPODTCTRL */
798 #define MMDC_MPODTCTRL_ODT_RD_ACT_EN_MASK	((0x1 << MMDC_MPODTCTRL_ODT_RD_ACT_EN))
799 #define MMDC_MPODTCTRL_ODT_RD_PAS_EN_MASK	((0x1 << MMDC_MPODTCTRL_ODT_RD_PAS_EN))
800 #define MMDC_MPODTCTRL_ODT_WR_ACT_EN_MASK	((0x1 << MMDC_MPODTCTRL_ODT_WR_ACT_EN))
801 #define MMDC_MPODTCTRL_ODT_WR_PAS_EN_MASK	((0x1 << MMDC_MPODTCTRL_ODT_WR_PAS_EN))
802 
803 /* MAPSR */
804 #define MMDC_MAPSR_DVACK_MASK		((0x1 << MMDC_MAPSR_DVACK))
805 #define MMDC_MAPSR_LPACK_MASK		((0x1 << MMDC_MAPSR_LPACK))
806 #define MMDC_MAPSR_DVFS_MASK		((0x1 << MMDC_MAPSR_DVFS))
807 #define MMDC_MAPSR_LPMD_MASK		((0x1 << MMDC_MAPSR_LPMD))
808 
809 /* MAARCR */
810 #define MMDC_MAARCR_ARCR_EXC_ERR_EN_MASK	((0x1 << MMDC_MAARCR_ARCR_EXC_ERR_EN))
811 
812 /* MPZQLP2CTL */
813 #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS_MASK	((0x7f  << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS))
814 #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL_MASK	((0xff  << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL))
815 #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT_MASK	((0x1ff << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT))
816 
817 /* MDCFG3LP */
818 #define MMDC_MDCFG3LP_tRC_LP_MASK	((0x3f  << MMDC_MDCFG3LP_tRC_LP))
819 #define MMDC_MDCFG3LP_tRCD_LP_MASK	((0xf   << MMDC_MDCFG3LP_tRCD_LP))
820 #define MMDC_MDCFG3LP_tRPpb_LP_MASK	((0xf   << MMDC_MDCFG3LP_tRPpb_LP))
821 #define MMDC_MDCFG3LP_tRPab_LP_MASK	((0xf   << MMDC_MDCFG3LP_tRPab_LP))
822 
823 /* MDOR */
824 #define MMDC_MDOR_tXPR_MASK		((0xff  << MMDC_MDOR_tXPR))
825 #define MMDC_MDOR_SDE_to_RST_MASK	((0x3f  << MMDC_MDOR_SDE_to_RST))
826 #define MMDC_MDOR_RST_to_CKE_MASK	((0x3f  << MMDC_MDOR_RST_to_CKE))
827 
828 /* MDCFG0 */
829 #define MMDC_MDCFG0_tRFC_MASK		((0xff  << MMDC_MDCFG0_tRFC))
830 #define MMDC_MDCFG0_tXS_MASK		((0xff  << MMDC_MDCFG0_tXS))
831 #define MMDC_MDCFG0_tXP_MASK		((0x7   << MMDC_MDCFG0_tXP))
832 #define MMDC_MDCFG0_tXPDLL_MASK		((0xf   << MMDC_MDCFG0_tXPDLL))
833 #define MMDC_MDCFG0_tFAW_MASK		((0x1f  << MMDC_MDCFG0_tFAW))
834 #define MMDC_MDCFG0_tCL_MASK		((0xf   << MMDC_MDCFG0_tCL))
835 
836 /* MDCFG1 */
837 #define MMDC_MDCFG1_tRCD_MASK		((0x7   << MMDC_MDCFG1_tRCD))
838 #define MMDC_MDCFG1_tRP_MASK		((0x7   << MMDC_MDCFG1_tRP))
839 #define MMDC_MDCFG1_tRC_MASK		((0x1f  << MMDC_MDCFG1_tRC))
840 #define MMDC_MDCFG1_tRAS_MASK		((0x1f  << MMDC_MDCFG1_tRAS))
841 #define MMDC_MDCFG1_tRPA_MASK		((0x1   << MMDC_MDCFG1_tRPA))
842 #define MMDC_MDCFG1_tWR_MASK		((0x7   << MMDC_MDCFG1_tWR))
843 #define MMDC_MDCFG1_tMRD_MASK		((0xf   << MMDC_MDCFG1_tMRD))
844 #define MMDC_MDCFG1_tCWL_MASK		((0x7   << MMDC_MDCFG1_tCWL))
845 
846 /* MDCFG2 */
847 #define MMDC_MDCFG2_tDLLK_MASK		((0x1ff << MMDC_MDCFG2_tDLLK))
848 #define MMDC_MDCFG2_tRTP_MASK		((0x7   << MMDC_MDCFG2_tRTP))
849 #define MMDC_MDCFG2_tWTR_MASK		((0x7   << MMDC_MDCFG2_tWTR))
850 #define MMDC_MDCFG2_tRRD_MASK		((0x7   << MMDC_MDCFG2_tRRD))
851 
852 /* MDRWD */
853 #define MMDC_MDRWD_tDAI_MASK		((0x1fff << MMDC_MDRWD_tDAI))
854 #define MMDC_MDRWD_RTW_SAME_MASK	((0x7    << MMDC_MDRWD_RTW_SAME))
855 #define MMDC_MDRWD_WTR_DIFF_MASK	((0x7    << MMDC_MDRWD_WTR_DIFF))
856 #define MMDC_MDRWD_WTW_DIFF_MASK	((0x7    << MMDC_MDRWD_WTW_DIFF))
857 #define MMDC_MDRWD_RTW_DIFF_MASK	((0x7    << MMDC_MDRWD_RTW_DIFF))
858 #define MMDC_MDRWD_RTR_DIFF_MASK	((0x7    << MMDC_MDRWD_RTR_DIFF))
859 
860 /* MDPDC */
861 #define MMDC_MDPDC_PRCT_1_MASK		((0x7    << MMDC_MDPDC_PRCT_1))
862 #define MMDC_MDPDC_PRCT_0_MASK		((0x7    << MMDC_MDPDC_PRCT_0))
863 #define MMDC_MDPDC_tCKE_MASK		((0x7    << MMDC_MDPDC_tCKE))
864 #define MMDC_MDPDC_PWDT_1_MASK		((0xf    << MMDC_MDPDC_PWDT_1))
865 #define MMDC_MDPDC_PWDT_0_MASK		((0xf    << MMDC_MDPDC_PWDT_0))
866 #define MMDC_MDPDC_SLOW_PD_MASK		((0x1    << MMDC_MDPDC_SLOW_PD))
867 #define MMDC_MDPDC_BOTH_CS_PD_MASK	((0x1    << MMDC_MDPDC_BOTH_CS_PD))
868 #define MMDC_MDPDC_tCKSRX_MASK		((0x7    << MMDC_MDPDC_tCKSRX))
869 #define MMDC_MDPDC_tCKSRE_MASK		((0x7    << MMDC_MDPDC_tCKSRE))
870 
871 /* MDASP */
872 #define MMDC_MDASP_CS0_END_MASK		((0x7f << MMDC_MDASP_CS0_END))
873 
874 /* MAEXIDR0 */
875 #define MMDC_MAEXIDR0_EXC_ID_MONITOR1_MASK	((0xffff << MMDC_MAEXIDR0_EXC_ID_MONITOR1))
876 #define MMDC_MAEXIDR0_EXC_ID_MONITOR0_MASK	((0xffff << MMDC_MAEXIDR0_EXC_ID_MONITOR0))
877 
878 /* MAEXIDR1 */
879 #define MMDC_MAEXIDR1_EXC_ID_MONITOR3_MASK	((0xffff << MMDC_MAEXIDR1_EXC_ID_MONITOR3))
880 #define MMDC_MAEXIDR1_EXC_ID_MONITOR2_MASK	((0xffff << MMDC_MAEXIDR1_EXC_ID_MONITOR2))
881 
882 /* MPWRDLCTL */
883 #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3_MASK	((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3))
884 #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2_MASK	((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2))
885 #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1_MASK	((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1))
886 #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0_MASK	((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0))
887 
888 /* MPRDDLCTL */
889 #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3_MASK	((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3))
890 #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2_MASK	((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2))
891 #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1_MASK	((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1))
892 #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0_MASK	((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0))
893 
894 /* MPWRDQBY0DL */
895 #define MMDC_MPWRDQBY0DL_WR_DM0_DEL_MASK	((0x3f  << MMDC_MPWRDQBY0DL_WR_DM0_DEL))
896 #define MMDC_MPWRDQBY0DL_WR_DQ7_DEL_MASK	((0x3f  << MMDC_MPWRDQBY0DL_WR_DQ7_DEL))
897 #define MMDC_MPWRDQBY0DL_WR_DQ6_DEL_MASK	((0x3f  << MMDC_MPWRDQBY0DL_WR_DQ6_DEL))
898 #define MMDC_MPWRDQBY0DL_WR_DQ5_DEL_MASK	((0x3f  << MMDC_MPWRDQBY0DL_WR_DQ5_DEL))
899 #define MMDC_MPWRDQBY0DL_WR_DQ4_DEL_MASK	((0x3f  << MMDC_MPWRDQBY0DL_WR_DQ4_DEL))
900 #define MMDC_MPWRDQBY0DL_WR_DQ3_DEL_MASK	((0x3f  << MMDC_MPWRDQBY0DL_WR_DQ3_DEL))
901 #define MMDC_MPWRDQBY0DL_WR_DQ2_DEL_MASK	((0x3f  << MMDC_MPWRDQBY0DL_WR_DQ2_DEL))
902 #define MMDC_MPWRDQBY0DL_WR_DQ1_DEL_MASK	((0x3f  << MMDC_MPWRDQBY0DL_WR_DQ1_DEL))
903 #define MMDC_MPWRDQBY0DL_WR_DQ0_DEL_MASK	((0x3f  << MMDC_MPWRDQBY0DL_WR_DQ0_DEL))
904 
905 /* MPWRDQBY1DL */
906 #define MMDC_MPWRDQBY1DL_WR_DM1_DEL_MASK	((0x3f  << MMDC_MPWRDQBY1DL_WR_DM1_DEL))
907 #define MMDC_MPWRDQBY1DL_WR_DQ15_DEL_MASK	((0x3f  << MMDC_MPWRDQBY1DL_WR_DQ15_DEL))
908 #define MMDC_MPWRDQBY1DL_WR_DQ14_DEL_MASK	((0x3f  << MMDC_MPWRDQBY1DL_WR_DQ14_DEL))
909 #define MMDC_MPWRDQBY1DL_WR_DQ13_DEL_MASK	((0x3f  << MMDC_MPWRDQBY1DL_WR_DQ13_DEL))
910 #define MMDC_MPWRDQBY1DL_WR_DQ12_DEL_MASK	((0x3f  << MMDC_MPWRDQBY1DL_WR_DQ12_DEL))
911 #define MMDC_MPWRDQBY1DL_WR_DQ11_DEL_MASK	((0x3f  << MMDC_MPWRDQBY1DL_WR_DQ11_DEL))
912 #define MMDC_MPWRDQBY1DL_WR_DQ10_DEL_MASK	((0x3f  << MMDC_MPWRDQBY1DL_WR_DQ10_DEL))
913 #define MMDC_MPWRDQBY1DL_WR_DQ9_DEL_MASK	((0x3f  << MMDC_MPWRDQBY1DL_WR_DQ9_DEL))
914 #define MMDC_MPWRDQBY1DL_WR_DQ8_DEL_MASK	((0x3f  << MMDC_MPWRDQBY1DL_WR_DQ8_DEL))
915 
916 /* MPWRDQBY2DL */
917 #define MMDC_MPWRDQBY2DL_WR_DM2_DEL_MASK	((0x3f  << MMDC_MPWRDQBY2DL_WR_DM2_DEL))
918 #define MMDC_MPWRDQBY2DL_WR_DQ23_DEL_MASK	((0x3f  << MMDC_MPWRDQBY2DL_WR_DQ23_DEL))
919 #define MMDC_MPWRDQBY2DL_WR_DQ22_DEL_MASK	((0x3f  << MMDC_MPWRDQBY2DL_WR_DQ22_DEL))
920 #define MMDC_MPWRDQBY2DL_WR_DQ21_DEL_MASK	((0x3f  << MMDC_MPWRDQBY2DL_WR_DQ21_DEL))
921 #define MMDC_MPWRDQBY2DL_WR_DQ20_DEL_MASK	((0x3f  << MMDC_MPWRDQBY2DL_WR_DQ20_DEL))
922 #define MMDC_MPWRDQBY2DL_WR_DQ19_DEL_MASK	((0x3f  << MMDC_MPWRDQBY2DL_WR_DQ19_DEL))
923 #define MMDC_MPWRDQBY2DL_WR_DQ18_DEL_MASK	((0x3f  << MMDC_MPWRDQBY2DL_WR_DQ18_DEL))
924 #define MMDC_MPWRDQBY2DL_WR_DQ17_DEL_MASK	((0x3f  << MMDC_MPWRDQBY2DL_WR_DQ17_DEL))
925 #define MMDC_MPWRDQBY2DL_WR_DQ16_DEL_MASK	((0x3f  << MMDC_MPWRDQBY2DL_WR_DQ16_DEL))
926 
927 /* MPWRDQBY3DL */
928 #define MMDC_MPWRDQBY3DL_WR_DM3_DEL_MASK	((0x3f  << MMDC_MPWRDQBY3DL_WR_DM3_DEL))
929 #define MMDC_MPWRDQBY3DL_WR_DQ31_DEL_MASK	((0x3f  << MMDC_MPWRDQBY3DL_WR_DQ31_DEL))
930 #define MMDC_MPWRDQBY3DL_WR_DQ30_DEL_MASK	((0x3f  << MMDC_MPWRDQBY3DL_WR_DQ30_DEL))
931 #define MMDC_MPWRDQBY3DL_WR_DQ29_DEL_MASK	((0x3f  << MMDC_MPWRDQBY3DL_WR_DQ29_DEL))
932 #define MMDC_MPWRDQBY3DL_WR_DQ28_DEL_MASK	((0x3f  << MMDC_MPWRDQBY3DL_WR_DQ28_DEL))
933 #define MMDC_MPWRDQBY3DL_WR_DQ27_DEL_MASK	((0x3f  << MMDC_MPWRDQBY3DL_WR_DQ27_DEL))
934 #define MMDC_MPWRDQBY3DL_WR_DQ26_DEL_MASK	((0x3f  << MMDC_MPWRDQBY3DL_WR_DQ26_DEL))
935 #define MMDC_MPWRDQBY3DL_WR_DQ25_DEL_MASK	((0x3f  << MMDC_MPWRDQBY3DL_WR_DQ25_DEL))
936 #define MMDC_MPWRDQBY3DL_WR_DQ24_DEL_MASK	((0x3f  << MMDC_MPWRDQBY3DL_WR_DQ24_DEL))
937 
938 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
939 
940 #include <asm/types.h>
941 
942 struct fuse_word {
943 	u32	fuse;
944 	u32	rsvd[3];
945 };
946 
947 struct ocotp_regs {
948 	u32	ctrl;
949 	u32	ctrl_set;
950 	u32	ctrl_clr;
951 	u32	ctrl_tog;
952 	u32	pdn;
953 	u32	rsvd0[3];
954 	u32	data;
955 	u32	rsvd1[3];
956 	u32	read_ctrl;
957 	u32	rsvd2[3];
958 	u32	read_fuse_data;
959 	u32	rsvd3[3];
960 	u32	sw_sticky;
961 	u32	rsvd4[3];
962 	u32	scs;
963 	u32	scs_set;
964 	u32	scs_clr;
965 	u32	scs_tog;
966 	u32	out_status;
967 	u32	out_status_set;
968 	u32	out_status_clr;
969 	u32	out_status_tog;
970 	u32	startword;
971 	u32	rsvd5[3];
972 	u32	version;
973 	u32	rsvd6[19];
974 	struct	fuse_word mem_repair[8];
975 	u32	rsvd7[0xa8];
976 
977 	/* fuse banks */
978 	struct fuse_bank {
979 		u32	fuse_regs[0x20];
980 	} bank[0];
981 };
982 
983 struct fuse_bank1_regs {
984 	u32	lock0;
985 	u32	rsvd0[3];
986 	u32	lock1;
987 	u32	rsvd1[3];
988 	u32	lock2;
989 	u32	rsvd2[3];
990 	u32	cfg0;
991 	u32	rsvd3[3];
992 	u32	cfg1;
993 	u32	rsvd4[3];
994 	u32	cfg2;
995 	u32	rsvd5[3];
996 	u32	cfg3;
997 	u32	rsvd6[3];
998 	u32	cfg4;
999 	u32	rsvd7[3];
1000 };
1001 
1002 struct fuse_bank2_regs {
1003 	struct fuse_word boot[8];
1004 };
1005 
1006 struct fuse_bank3_regs {
1007 	u32	mem0;
1008 	u32	rsvd0[3];
1009 	u32	mem1;
1010 	u32	rsvd1[3];
1011 	u32	mem2;
1012 	u32	rsvd2[3];
1013 	u32	mem3;
1014 	u32	rsvd3[3];
1015 	u32	ana0;
1016 	u32	rsvd4[3];
1017 	u32	ana1;
1018 	u32	rsvd5[3];
1019 	u32	ana2;
1020 	u32	rsvd6[3];
1021 	u32	ana3;
1022 	u32	rsvd7[3];
1023 };
1024 
1025 struct fuse_bank7_regs {
1026 	u32	sjc_resp0;
1027 	u32	rsvd0[3];
1028 	u32	sjc_resp1;
1029 	u32	rsvd1[3];
1030 	u32	gp0;
1031 	u32	rsvd2[3];
1032 	u32	gp1;
1033 	u32	rsvd3[3];
1034 	u32	gp2;
1035 	u32	rsvd4[3];
1036 	u32	gp3;
1037 	u32	rsvd5[3];
1038 	u32	gp4;
1039 	u32	rsvd6[3];
1040 	u32	gp5;
1041 	u32	rsvd7[3];
1042 };
1043 
1044 struct usbphy_regs {
1045 	u32	usbphy_pwd;			/* 0x000 */
1046 	u32	usbphy_pwd_set;			/* 0x004 */
1047 	u32	usbphy_pwd_clr;			/* 0x008 */
1048 	u32	usbphy_pwd_tog;			/* 0x00c */
1049 	u32	usbphy_tx;			/* 0x010 */
1050 	u32	usbphy_tx_set;			/* 0x014 */
1051 	u32	usbphy_tx_clr;			/* 0x018 */
1052 	u32	usbphy_tx_tog;			/* 0x01c */
1053 	u32	usbphy_rx;			/* 0x020 */
1054 	u32	usbphy_rx_set;			/* 0x024 */
1055 	u32	usbphy_rx_clr;			/* 0x028 */
1056 	u32	usbphy_rx_tog;			/* 0x02c */
1057 	u32	usbphy_ctrl;			/* 0x030 */
1058 	u32	usbphy_ctrl_set;		/* 0x034 */
1059 	u32	usbphy_ctrl_clr;		/* 0x038 */
1060 	u32	usbphy_ctrl_tog;		/* 0x03c */
1061 	u32	usbphy_status;			/* 0x040 */
1062 	u32	reserved0[3];
1063 	u32	usbphy_debug0;			/* 0x050 */
1064 	u32	usbphy_debug0_set;		/* 0x054 */
1065 	u32	usbphy_debug0_clr;		/* 0x058 */
1066 	u32	usbphy_debug0_tog;		/* 0x05c */
1067 	u32	reserved1[4];
1068 	u32	usbphy_debug1;			/* 0x070 */
1069 	u32	usbphy_debug1_set;		/* 0x074 */
1070 	u32	usbphy_debug1_clr;		/* 0x078 */
1071 	u32	usbphy_debug1_tog;		/* 0x07c */
1072 	u32	usbphy_version;			/* 0x080 */
1073 	u32	reserved2[7];
1074 	u32	usb1_pll_480_ctrl;		/* 0x0a0 */
1075 	u32	usb1_pll_480_ctrl_set;		/* 0x0a4 */
1076 	u32	usb1_pll_480_ctrl_clr;		/* 0x0a8 */
1077 	u32	usb1_pll_480_ctrl_tog;		/* 0x0ac */
1078 	u32	reserved3[4];
1079 	u32	usb1_vbus_detect;		/* 0xc0 */
1080 	u32	usb1_vbus_detect_set;		/* 0xc4 */
1081 	u32	usb1_vbus_detect_clr;		/* 0xc8 */
1082 	u32	usb1_vbus_detect_tog;		/* 0xcc */
1083 	u32	usb1_vbus_det_stat;		/* 0xd0 */
1084 	u32	reserved4[3];
1085 	u32	usb1_chrg_detect;		/* 0xe0 */
1086 	u32	usb1_chrg_detect_set;		/* 0xe4 */
1087 	u32	usb1_chrg_detect_clr;		/* 0xe8 */
1088 	u32	usb1_chrg_detect_tog;		/* 0xec */
1089 	u32	usb1_chrg_det_stat;		/* 0xf0 */
1090 	u32	reserved5[3];
1091 	u32	usbphy_anactrl;			/* 0x100 */
1092 	u32	usbphy_anactrl_set;		/* 0x104 */
1093 	u32	usbphy_anactrl_clr;		/* 0x108 */
1094 	u32	usbphy_anactrl_tog;		/* 0x10c */
1095 	u32	usb1_loopback;			/* 0x110 */
1096 	u32	usb1_loopback_set;		/* 0x114 */
1097 	u32	usb1_loopback_clr;		/* 0x118 */
1098 	u32	usb1_loopback_tog;		/* 0x11c */
1099 	u32	usb1_loopback_hsfscnt;		/* 0x120 */
1100 	u32	usb1_loopback_hsfscnt_set;	/* 0x124 */
1101 	u32	usb1_loopback_hsfscnt_clr;	/* 0x128 */
1102 	u32	usb1_loopback_hsfscnt_tog;	/* 0x12c */
1103 	u32	usphy_trim_override_en;		/* 0x130 */
1104 	u32	usphy_trim_override_en_set;	/* 0x134 */
1105 	u32	usphy_trim_override_en_clr;	/* 0x138 */
1106 	u32	usphy_trim_override_en_tog;	/* 0x13c */
1107 	u32	usb1_pfda_ctrl1;		/* 0x140 */
1108 	u32	usb1_pfda_ctrl1_set;		/* 0x144 */
1109 	u32	usb1_pfda_ctrl1_clr;		/* 0x148 */
1110 	u32	usb1_pfda_ctrl1_tog;		/* 0x14c */
1111 };
1112 
1113 
1114 #define	is_boot_from_usb(void)		(!(readl(USB_PHY0_BASE_ADDR) & (1<<20)))
1115 #define	disconnect_from_pc(void)	writel(0x0, USBOTG0_RBASE + 0x140)
1116 
1117 #endif
1118 
1119 #endif /* _MX7ULP_REGS_H_*/
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