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Searched refs:MMDC_P0_BASE_ADDR (Results 1 – 7 of 7) sorted by relevance

/external/u-boot/board/wandboard/
Dspl.c319 writel(0x00008000, MMDC_P0_BASE_ADDR + 0x01c); in spl_dram_init_imx6qp_lpddr3()
321 writel(0xa1390003, MMDC_P0_BASE_ADDR + 0x800); in spl_dram_init_imx6qp_lpddr3()
323 writel(0x00060004, MMDC_P0_BASE_ADDR + 0x80c); in spl_dram_init_imx6qp_lpddr3()
324 writel(0x000B0004, MMDC_P0_BASE_ADDR + 0x810); in spl_dram_init_imx6qp_lpddr3()
331 writel(0x03040314, MMDC_P0_BASE_ADDR + 0x83c); in spl_dram_init_imx6qp_lpddr3()
332 writel(0x03080300, MMDC_P0_BASE_ADDR + 0x840); in spl_dram_init_imx6qp_lpddr3()
335 writel(0x4034363A, MMDC_P0_BASE_ADDR + 0x848); in spl_dram_init_imx6qp_lpddr3()
337 writel(0x3E3E4046, MMDC_P0_BASE_ADDR + 0x850); in spl_dram_init_imx6qp_lpddr3()
339 writel(0x33333333, MMDC_P0_BASE_ADDR + 0x81c); in spl_dram_init_imx6qp_lpddr3()
340 writel(0x33333333, MMDC_P0_BASE_ADDR + 0x820); in spl_dram_init_imx6qp_lpddr3()
[all …]
/external/u-boot/arch/arm/mach-imx/mx6/
Dddr.c19 struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR; in reset_read_data_fifos()
31 struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR; in precharge_all()
52 struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR; in force_delay_measurement()
106 struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR; in mmdc_do_write_level_calibration()
250 struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR; in mmdc_do_dqs_calibration()
1012 mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR; in mx6_lpddr2_cfg()
1240 mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR; in mx6_ddr3_cfg()
1529 struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR; in mmdc_read_calibration()
/external/u-boot/board/freescale/mx6ullevk/
Dplugin.S49 ldr r0, =MMDC_P0_BASE_ADDR
/external/u-boot/board/freescale/mx6sllevk/
Dplugin.S42 ldr r0, =MMDC_P0_BASE_ADDR
/external/u-boot/arch/arm/mach-imx/
Dcpu.c91 #define MEMCTL_BASE MMDC_P0_BASE_ADDR
/external/u-boot/board/freescale/mx6qarm2/
Dimximage_mx6dl.cfg139 /* MMDC_P0_BASE_ADDR = 0x021b0000 */
/external/u-boot/arch/arm/include/asm/arch-mx6/
Dimx-regs.h267 #define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000) macro