Searched refs:MMDC_P1_BASE_ADDR (Results 1 – 4 of 4) sorted by relevance
| /external/u-boot/board/wandboard/ |
| D | spl.c | 325 writel(0x00000004, MMDC_P1_BASE_ADDR + 0x80c); in spl_dram_init_imx6qp_lpddr3()
326 writel(0x00000000, MMDC_P1_BASE_ADDR + 0x810); in spl_dram_init_imx6qp_lpddr3()
333 writel(0x03000310, MMDC_P1_BASE_ADDR + 0x83c); in spl_dram_init_imx6qp_lpddr3()
334 writel(0x0268023C, MMDC_P1_BASE_ADDR + 0x840); in spl_dram_init_imx6qp_lpddr3()
336 writel(0x36302C3C, MMDC_P1_BASE_ADDR + 0x848); in spl_dram_init_imx6qp_lpddr3()
338 writel(0x483A4844, MMDC_P1_BASE_ADDR + 0x850); in spl_dram_init_imx6qp_lpddr3()
343 writel(0x33333333, MMDC_P1_BASE_ADDR + 0x81c); in spl_dram_init_imx6qp_lpddr3()
344 writel(0x33333333, MMDC_P1_BASE_ADDR + 0x820); in spl_dram_init_imx6qp_lpddr3()
345 writel(0x33333333, MMDC_P1_BASE_ADDR + 0x824); in spl_dram_init_imx6qp_lpddr3()
346 writel(0x33333333, MMDC_P1_BASE_ADDR + 0x828); in spl_dram_init_imx6qp_lpddr3()
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| /external/u-boot/arch/arm/mach-imx/mx6/ |
| D | ddr.c | 53 struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR; in force_delay_measurement()
107 struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR; in mmdc_do_write_level_calibration()
251 struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR; in mmdc_do_dqs_calibration()
1242 mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR; in mx6_ddr3_cfg()
1530 struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR; in mmdc_read_calibration()
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| /external/u-boot/board/freescale/mx6qarm2/ |
| D | imximage_mx6dl.cfg | 140 /* MMDC_P1_BASE_ADDR = 0x021b4000 */
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| /external/u-boot/arch/arm/include/asm/arch-mx6/ |
| D | imx-regs.h | 277 #define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) macro
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