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Searched refs:MO2 (Results 1 – 24 of 24) sorted by relevance

/external/swiftshader/third_party/LLVM/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp62 const MCOperand &MO2 = MI->getOperand(2); in printInst() local
72 O << ", " << getRegisterName(MO2.getReg()); in printInst()
82 const MCOperand &MO2 = MI->getOperand(2); in printInst() local
84 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm())); in printInst()
91 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) { in printInst()
96 O << ", #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())); in printInst()
243 const MCOperand &MO2 = MI->getOperand(OpNum+1); in printSORegRegOperand() local
254 O << ' ' << getRegisterName(MO2.getReg()); in printSORegRegOperand()
261 const MCOperand &MO2 = MI->getOperand(OpNum+1); in printSORegImmOperand() local
266 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm()); in printSORegImmOperand()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp90 const MCOperand &MO2 = MI->getOperand(2); in printInst() local
103 printRegName(O, MO2.getReg()); in printInst()
113 const MCOperand &MO2 = MI->getOperand(2); in printInst() local
115 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm())); in printInst()
124 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) { in printInst()
130 << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())) << markup(">"); in printInst()
358 const MCOperand &MO2 = MI->getOperand(OpNum + 1); in printSORegRegOperand() local
370 printRegName(O, MO2.getReg()); in printSORegRegOperand()
378 const MCOperand &MO2 = MI->getOperand(OpNum + 1); in printSORegImmOperand() local
383 printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()), in printSORegImmOperand()
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/external/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp82 const MCOperand &MO2 = MI->getOperand(2); in printInst() local
95 printRegName(O, MO2.getReg()); in printInst()
105 const MCOperand &MO2 = MI->getOperand(2); in printInst() local
107 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm())); in printInst()
116 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) { in printInst()
122 << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())) << markup(">"); in printInst()
346 const MCOperand &MO2 = MI->getOperand(OpNum + 1); in printSORegRegOperand() local
358 printRegName(O, MO2.getReg()); in printSORegRegOperand()
366 const MCOperand &MO2 = MI->getOperand(OpNum + 1); in printSORegImmOperand() local
371 printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()), in printSORegImmOperand()
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/external/llvm/lib/Target/X86/
DX86OptimizeLEAs.cpp56 const MachineOperand &MO2);
61 const MachineOperand &MO2);
182 const MachineOperand &MO2) { in isIdenticalOp() argument
183 return MO1.isIdenticalTo(MO2) && in isIdenticalOp()
196 const MachineOperand &MO2) { in isSimilarDispOp() argument
197 assert(isValidDispOp(MO1) && isValidDispOp(MO2) && in isSimilarDispOp()
199 return (MO1.isImm() && MO2.isImm()) || in isSimilarDispOp()
200 (MO1.isCPI() && MO2.isCPI() && MO1.getIndex() == MO2.getIndex()) || in isSimilarDispOp()
201 (MO1.isJTI() && MO2.isJTI() && MO1.getIndex() == MO2.getIndex()) || in isSimilarDispOp()
202 (MO1.isSymbol() && MO2.isSymbol() && in isSimilarDispOp()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86OptimizeLEAs.cpp66 const MachineOperand &MO2);
71 const MachineOperand &MO2);
200 const MachineOperand &MO2) { in isIdenticalOp() argument
201 return MO1.isIdenticalTo(MO2) && in isIdenticalOp()
214 const MachineOperand &MO2) { in isSimilarDispOp() argument
215 assert(isValidDispOp(MO1) && isValidDispOp(MO2) && in isSimilarDispOp()
217 return (MO1.isImm() && MO2.isImm()) || in isSimilarDispOp()
218 (MO1.isCPI() && MO2.isCPI() && MO1.getIndex() == MO2.getIndex()) || in isSimilarDispOp()
219 (MO1.isJTI() && MO2.isJTI() && MO1.getIndex() == MO2.getIndex()) || in isSimilarDispOp()
220 (MO1.isSymbol() && MO2.isSymbol() && in isSimilarDispOp()
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/external/capstone/arch/ARM/
DARMInstPrinter.c446 MCOperand *MO2 = MCInst_getOperand(MI, 2); in ARM_printInst() local
471 printRegName(MI->csh, O, MCOperand_getReg(MO2)); in ARM_printInst()
474 …->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO2); in ARM_printInst()
485 MCOperand *MO2 = MCInst_getOperand(MI, 2); in ARM_printInst() local
487 …Stream_concat0(O, ARM_AM_getShiftOpcStr(ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)))); in ARM_printInst()
507 if (ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)) == ARM_AM_rrx) { in ARM_printInst()
513 tmp = translateShiftImm(getSORegOffset((unsigned int)MCOperand_getImm(MO2))); in ARM_printInst()
520 (arm_shifter)ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)); in ARM_printInst()
580 MCOperand *MO2 = MCInst_getOperand(MI, 4); in ARM_printInst() local
581 if ((getAM2Op((unsigned int)MCOperand_getImm(MO2)) == ARM_AM_add && in ARM_printInst()
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/
DARMMCCodeEmitter.cpp691 const MCOperand &MO2 = MI.getOperand(OpIdx + 1); in getThumbAddrModeRegRegOpValue() local
693 unsigned Rm = getARMRegisterNumbering(MO2.getReg()); in getThumbAddrModeRegRegOpValue()
895 const MCOperand &MO2 = MI.getOperand(OpIdx+2); in getLdStSORegOpValue() local
898 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()); in getLdStSORegOpValue()
899 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add; in getLdStSORegOpValue()
900 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm()); in getLdStSORegOpValue()
995 const MCOperand &MO2 = MI.getOperand(OpIdx+2); in getAddrMode3OpValue() local
997 unsigned Imm = MO2.getImm(); in getAddrMode3OpValue()
1100 const MCOperand &MO2 = MI.getOperand(OpIdx + 2); in getSORegRegOpValue() local
1101 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); in getSORegRegOpValue()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/MCTargetDesc/
DARMMCCodeEmitter.cpp875 const MCOperand &MO2 = MI.getOperand(OpIdx + 1); in getThumbAddrModeRegRegOpValue() local
877 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg()); in getThumbAddrModeRegRegOpValue()
1082 const MCOperand &MO2 = MI.getOperand(OpIdx+2); in getLdStSORegOpValue() local
1085 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()); in getLdStSORegOpValue()
1086 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add; in getLdStSORegOpValue()
1087 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm()); in getLdStSORegOpValue()
1176 const MCOperand &MO2 = MI.getOperand(OpIdx+2); in getAddrMode3OpValue() local
1191 unsigned Imm = MO2.getImm(); in getAddrMode3OpValue()
1339 const MCOperand &MO2 = MI.getOperand(OpIdx + 2); in getSORegRegOpValue() local
1340 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); in getSORegRegOpValue()
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/external/llvm/lib/Target/ARM/MCTargetDesc/
DARMMCCodeEmitter.cpp864 const MCOperand &MO2 = MI.getOperand(OpIdx + 1); in getThumbAddrModeRegRegOpValue() local
866 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg()); in getThumbAddrModeRegRegOpValue()
1071 const MCOperand &MO2 = MI.getOperand(OpIdx+2); in getLdStSORegOpValue() local
1074 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()); in getLdStSORegOpValue()
1075 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add; in getLdStSORegOpValue()
1076 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm()); in getLdStSORegOpValue()
1165 const MCOperand &MO2 = MI.getOperand(OpIdx+2); in getAddrMode3OpValue() local
1180 unsigned Imm = MO2.getImm(); in getAddrMode3OpValue()
1328 const MCOperand &MO2 = MI.getOperand(OpIdx + 2); in getSORegRegOpValue() local
1329 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); in getSORegRegOpValue()
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMCodeEmitter.cpp926 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2); in getMachineSoRegOpValue() local
927 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); in getMachineSoRegOpValue()
968 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0); in getMachineSoRegOpValue()
973 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7; in getMachineSoRegOpValue()
1145 const MachineOperand &MO2 = MI.getOperand(OpIdx); in emitLoadStoreInstruction() local
1152 if (!MO2.getReg()) { // is immediate in emitLoadStoreInstruction()
1162 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg())); in emitLoadStoreInstruction()
1164 Binary |= getARMRegisterNumbering(MO2.getReg()); in emitLoadStoreInstruction()
1216 const MachineOperand &MO2 = MI.getOperand(OpIdx); in emitMiscLoadStoreInstruction() local
1226 if (MO2.getReg()) { in emitMiscLoadStoreInstruction()
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DARMAsmPrinter.cpp907 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id in EmitJumpTable() local
914 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm()); in EmitJumpTable()
951 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id in EmitJump2Table() local
963 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm()); in EmitJump2Table()
/external/llvm/lib/CodeGen/
DScheduleDAGInstrs.cpp706 for (const MachineOperand &MO2 : MI->operands()) { in collectVRegUses() local
707 if (MO2.isReg() && MO2.isDef() && MO2.getReg() == Reg && !MO2.isDead()) { in collectVRegUses()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/AsmParser/
DHexagonAsmParser.cpp1226 MCOperand &MO2) { in makeCombineInst() argument
1231 TmpInst.addOperand(MO2); in makeCombineInst()
1587 MCOperand &MO2 = Inst.getOperand(2); in processInstruction() local
1589 if (MO2.getExpr()->evaluateAsAbsolute(Value)) { in processInstruction()
1594 Inst = makeCombineInst(Hexagon::A2_combineii, Rdd, MO1, MO2); in processInstruction()
1608 MCOperand &MO2 = Inst.getOperand(2); in processInstruction() local
1609 Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, MO1, MO2); in processInstruction()
/external/llvm/lib/Target/Hexagon/AsmParser/
DHexagonAsmParser.cpp1461 MCOperand &MO1, MCOperand &MO2) { in makeCombineInst() argument
1466 TmpInst.addOperand(MO2); in makeCombineInst()
1809 MCOperand &MO2 = Inst.getOperand(2); in processInstruction() local
1811 if (MO2.getExpr()->evaluateAsAbsolute(Value)) { in processInstruction()
1816 Inst = makeCombineInst(Hexagon::A2_combineii, Rdd, MO1, MO2); in processInstruction()
1830 MCOperand &MO2 = Inst.getOperand(2); in processInstruction() local
1831 Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, MO1, MO2); in processInstruction()
/external/llvm/lib/Target/Hexagon/
DHexagonAsmPrinter.cpp402 MCOperand &MO2 = MappedInst.getOperand(2); in HexagonProcessInstruction() local
403 MCExpr const *Expr = MO2.getExpr(); in HexagonProcessInstruction()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DR600InstrInfo.cpp953 MachineOperand &MO2 = Cond[2]; in reverseBranchCondition() local
954 switch (MO2.getReg()) { in reverseBranchCondition()
956 MO2.setReg(R600::PRED_SEL_ONE); in reverseBranchCondition()
959 MO2.setReg(R600::PRED_SEL_ZERO); in reverseBranchCondition()
DSIInstrInfo.cpp385 auto MO2 = *MI2.memoperands_begin(); in memOpsHaveSameBasePtr() local
386 if (MO1->getAddrSpace() != MO2->getAddrSpace()) in memOpsHaveSameBasePtr()
390 auto Base2 = MO2->getValue(); in memOpsHaveSameBasePtr()
/external/llvm/lib/Target/AMDGPU/
DR600InstrInfo.cpp964 MachineOperand &MO2 = Cond[2]; in ReverseBranchCondition() local
965 switch (MO2.getReg()) { in ReverseBranchCondition()
967 MO2.setReg(AMDGPU::PRED_SEL_ONE); in ReverseBranchCondition()
970 MO2.setReg(AMDGPU::PRED_SEL_ZERO); in ReverseBranchCondition()
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DLiveIntervalAnalysis.cpp315 MachineOperand &MO2 = mi->getOperand(i); in handleVirtualRegisterDef() local
316 if (MO2.isReg() && MO2.getReg() == interval.reg && MO2.getSubReg()) in handleVirtualRegisterDef()
317 MO2.setIsUndef(); in handleVirtualRegisterDef()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonAsmPrinter.cpp460 MCOperand &MO2 = MappedInst.getOperand(2); in HexagonProcessInstruction() local
461 MCExpr const *Expr = MO2.getExpr(); in HexagonProcessInstruction()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DMachineScheduler.cpp956 for (const MachineOperand &MO2 : MI.operands()) { in collectVRegUses() local
957 if (MO2.isReg() && MO2.isDef() && MO2.getReg() == Reg && !MO2.isDead()) { in collectVRegUses()
/external/honggfuzz/examples/apache-httpd/corpus_http2/
D179aaccfe25dca3c899610668cd59155.00021d24.honggfuzz.cov294 �;���*Ŭ82[w�����O+DPX�����$�H89�J�3Ռ��P2n�Z��MO2�e�>V�iT�EڪI%"J�c�?G�@��-�� �����d֑��x�…
/external/cldr/tools/java/org/unicode/cldr/util/data/external/
D2013-1_UNLOCODE_CodeListPart3.csv19641 ,"US","MO2","Melrose","Melrose","TN","--3-----","RL","0901",,"3607N 08647W",
D2013-1_UNLOCODE_CodeListPart1.csv39123 ,"FR","MO2","Moussan","Moussan","11","-----6--","RQ","0907",,"4314N 00257E",