/external/llvm/lib/Target/BPF/ |
D | BPFMCInstLower.cpp | 67 case MachineOperand::MO_RegisterMask: in Lower()
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/external/llvm/include/llvm/CodeGen/ |
D | MachineOperand.h | 59 MO_RegisterMask, ///< Mask of preserved registers. enumerator 254 bool isRegMask() const { return OpKind == MO_RegisterMask; } in isRegMask() 704 MachineOperand Op(MachineOperand::MO_RegisterMask); in CreateRegMask()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/BPF/ |
D | BPFMCInstLower.cpp | 72 case MachineOperand::MO_RegisterMask: in Lower()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/ |
D | SparcMCInstLower.cpp | 88 case MachineOperand::MO_RegisterMask: break; in LowerOperand()
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/external/llvm/lib/Target/Sparc/ |
D | SparcMCInstLower.cpp | 88 case MachineOperand::MO_RegisterMask: break; in LowerOperand()
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/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
D | MachineOperand.h | 64 MO_RegisterMask, ///< Mask of preserved registers. enumerator 335 bool isRegMask() const { return OpKind == MO_RegisterMask; } in isRegMask() 853 MachineOperand Op(MachineOperand::MO_RegisterMask); in CreateRegMask()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Nios2/ |
D | Nios2MCInstLower.cpp | 98 case MachineOperand::MO_RegisterMask: in LowerOperand()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/ |
D | RISCVMCInstLower.cpp | 72 case MachineOperand::MO_RegisterMask: in LowerRISCVMachineOperandToMCOperand()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARC/ |
D | ARCMCInstLower.cpp | 98 case MachineOperand::MO_RegisterMask: in LowerOperand()
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/external/llvm/lib/Target/XCore/ |
D | XCoreMCInstLower.cpp | 100 case MachineOperand::MO_RegisterMask: in LowerOperand()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/XCore/ |
D | XCoreMCInstLower.cpp | 97 case MachineOperand::MO_RegisterMask: in LowerOperand()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/ |
D | AVRMCInstLower.cpp | 93 case MachineOperand::MO_RegisterMask: in lowerInstruction()
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/external/llvm/lib/Target/MSP430/ |
D | MSP430MCInstLower.cpp | 151 case MachineOperand::MO_RegisterMask: in Lower()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/ |
D | LanaiMCInstLower.cpp | 115 case MachineOperand::MO_RegisterMask: in Lower()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/MSP430/ |
D | MSP430MCInstLower.cpp | 151 case MachineOperand::MO_RegisterMask: in Lower()
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/external/llvm/lib/Target/Lanai/ |
D | LanaiMCInstLower.cpp | 116 case MachineOperand::MO_RegisterMask: in Lower()
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/external/llvm/lib/Target/ARM/ |
D | ARMMCInstLower.cpp | 100 case MachineOperand::MO_RegisterMask: in lowerOperand()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
D | HexagonMCInstLower.cpp | 122 case MachineOperand::MO_RegisterMask: in HexagonLowerToMC()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
D | ARMMCInstLower.cpp | 117 case MachineOperand::MO_RegisterMask: in lowerOperand()
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/external/llvm/lib/Target/PowerPC/ |
D | PPCMCInstLower.cpp | 181 case MachineOperand::MO_RegisterMask: in LowerPPCMachineInstrToMCInst()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
D | PPCMCInstLower.cpp | 197 case MachineOperand::MO_RegisterMask: in LowerPPCMachineOperandToMCOperand()
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/external/llvm/lib/Target/AArch64/ |
D | AArch64MCInstLower.cpp | 174 case MachineOperand::MO_RegisterMask: in lowerOperand()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
D | MachineOperand.cpp | 292 case MachineOperand::MO_RegisterMask: in isIdenticalTo() 357 case MachineOperand::MO_RegisterMask: in hash_value() 846 case MachineOperand::MO_RegisterMask: { in print()
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/external/llvm/lib/Target/Mips/ |
D | MipsMCInstLower.cpp | 198 case MachineOperand::MO_RegisterMask: in LowerOperand()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
D | AArch64MCInstLower.cpp | 215 case MachineOperand::MO_RegisterMask: in lowerOperand()
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