| /external/llvm/lib/Target/AMDGPU/ |
| D | R600OptimizeVectorRegisters.cpp | 278 for (MachineInstr::mop_iterator MOp = RSI.Instr->operands_begin(), in tryMergeUsingCommonSlot() local
279 MOE = RSI.Instr->operands_end(); MOp != MOE; ++MOp) { in tryMergeUsingCommonSlot()
280 if (!MOp->isReg()) in tryMergeUsingCommonSlot()
282 if (PreviousRegSeqByReg[MOp->getReg()].empty()) in tryMergeUsingCommonSlot()
284 for (MachineInstr *MI : PreviousRegSeqByReg[MOp->getReg()]) { in tryMergeUsingCommonSlot()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | R600OptimizeVectorRegisters.cpp | 300 for (MachineInstr::mop_iterator MOp = RSI.Instr->operands_begin(), in tryMergeUsingCommonSlot() local
301 MOE = RSI.Instr->operands_end(); MOp != MOE; ++MOp) { in tryMergeUsingCommonSlot()
302 if (!MOp->isReg()) in tryMergeUsingCommonSlot()
304 if (PreviousRegSeqByReg[MOp->getReg()].empty()) in tryMergeUsingCommonSlot()
306 for (MachineInstr *MI : PreviousRegSeqByReg[MOp->getReg()]) { in tryMergeUsingCommonSlot()
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| /external/llvm/lib/Target/Mips/ |
| D | Mips16ISelDAGToDAG.cpp | 203 unsigned MOp; in trySelect() local
206 MOp = Mips::AdduRxRyRz16; in trySelect()
209 MOp = Mips::SubuRxRyRz16; in trySelect()
225 CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS, SDValue(AddCarry, 0)); in trySelect()
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| D | MipsSEISelDAGToDAG.h | 42 void selectAddESubE(unsigned MOp, SDValue InFlag, SDValue CmpLHS,
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| D | MipsSEISelDAGToDAG.cpp | 240 void MipsSEDAGToDAGISel::selectAddESubE(unsigned MOp, SDValue InFlag, in selectAddESubE() argument
279 CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS, SDValue(AddCarry, 0)); in selectAddESubE()
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| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsISelDAGToDAG.cpp | 217 unsigned MOp; in Select() local
220 MOp = Mips::ADDu; in Select()
223 MOp = Mips::SUBu; in Select()
236 return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, in Select()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86CmovConversion.cpp | 790 for (auto &MOp : NewMI->uses()) { in convertCmovInstsToBranches() local
791 if (!MOp.isReg()) in convertCmovInstsToBranches()
793 auto It = FalseBBRegRewriteTable.find(MOp.getReg()); in convertCmovInstsToBranches()
797 MOp.setReg(It->second); in convertCmovInstsToBranches()
803 MOp.setIsKill(false); in convertCmovInstsToBranches()
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| D | X86FlagsCopyLowering.cpp | 278 MI.operands(), [&](MachineOperand &MOp) { in splitBlock() argument
279 return MOp.isMBB() && MOp.getMBB() == &UnsplitSucc; in splitBlock()
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| D | X86ISelLowering.cpp | 27361 unsigned MOp, FOp; in EmitLoweredAtomicFP() local
27366 MOp = X86::MOVSSmr; in EmitLoweredAtomicFP()
27370 MOp = X86::MOVSDmr; in EmitLoweredAtomicFP()
27391 MIB = BuildMI(*BB, MI, DL, TII->get(MOp)); in EmitLoweredAtomicFP()
28509 for (auto &MOp : II.operands()) in EmitSjLjDispatchBlock() local
28510 if (MOp.isReg()) in EmitSjLjDispatchBlock()
28511 DefRegs[MOp.getReg()] = true; in EmitSjLjDispatchBlock()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | MachineInstr.cpp | 1107 MachineOperand &MOp = getOperand(j); in copyKillDeadInfo() local
1108 if (!MOp.isIdenticalTo(MO)) in copyKillDeadInfo()
1111 MOp.setIsKill(); in copyKillDeadInfo()
1113 MOp.setIsDead(); in copyKillDeadInfo()
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| /external/llvm/lib/CodeGen/ |
| D | PeepholeOptimizer.cpp | 1628 const MachineOperand &MOp = MI->getOperand(i); in runOnMachineFunction() local
1629 if (!MOp.isReg()) in runOnMachineFunction()
1631 unsigned FoldAsLoadDefReg = MOp.getReg(); in runOnMachineFunction()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | PeepholeOptimizer.cpp | 1761 const MachineOperand &MOp = MI->getOperand(i); in runOnMachineFunction() local
1762 if (!MOp.isReg()) in runOnMachineFunction()
1764 unsigned FoldAsLoadDefReg = MOp.getReg(); in runOnMachineFunction()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 23416 unsigned MOp, FOp; in EmitLoweredAtomicFP() local
23421 MOp = X86::MOVSSmr; in EmitLoweredAtomicFP()
23425 MOp = X86::MOVSDmr; in EmitLoweredAtomicFP()
23446 MIB = BuildMI(*BB, MI, DL, TII->get(MOp)); in EmitLoweredAtomicFP()
24147 for (auto &MOp : II.operands()) in EmitSjLjDispatchBlock() local
24148 if (MOp.isReg()) in EmitSjLjDispatchBlock()
24149 DefRegs[MOp.getReg()] = true; in EmitSjLjDispatchBlock()
|