Searched refs:MPLL (Results 1 – 8 of 8) sorted by relevance
36 case MPLL: in s5pc100_get_pll_clk()87 case MPLL: in s5pc110_get_pll_clk()107 if (pllreg == APLL || pllreg == MPLL) in s5pc110_get_pll_clk()206 d1_bus = get_pll_clk(MPLL) / (d1_bus_ratio + 1); in get_pclkd1()236 hclk = get_pll_clk(MPLL) / (hclk_sys_ratio + 1); in get_hclk_sys()
125 if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL || in exynos_get_pll_clk()195 case MPLL: in exynos4_get_pll_clk()225 case MPLL: in exynos4x12_get_pll_clk()256 case MPLL: in exynos5_get_pll_clk()279 if (pllreg == MPLL || pllreg == BPLL) { in exynos5_get_pll_clk()283 case MPLL: in exynos5_get_pll_clk()314 case MPLL: in exynos542x_get_pll_clk()437 sclk = exynos5_get_pll_clk(MPLL); in exynos5_get_periph_rate()528 sclk = exynos542x_get_pll_clk(MPLL); in exynos542x_get_periph_rate()652 sclk = get_pll_clk(MPLL); in exynos4_get_pwm_clk()[all …]
12 #define MPLL 1 macro
13 #define MPLL 2 macro
11 #define MPLL 1 macro
157 printf("MPLL Speed: %lu MHz\n", CLK_MHZ(rate(MPLL))); in soc_clk_dump()
55 samsung,pclk-name: parent clock identifier: 1(MPLL), 2(EPLL), 3(VPLL)
356 case MPLL: in pic32_get_rate()