/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/ |
D | X86BaseInfo.h | 215 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 enumerator 490 case X86II::MRM0r: case X86II::MRM1r: in getMemoryOperandNo()
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D | X86MCCodeEmitter.cpp | 578 case X86II::MRM0r: case X86II::MRM1r: in EmitVEXOpcodePrefix() 964 case X86II::MRM0r: case X86II::MRM1r: in EncodeInstruction()
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/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
D | X86InstrShiftRotate.td | 506 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1), 509 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src1), 512 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src1), 515 def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src1), 520 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2), 523 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2), 527 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2), 530 def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst), 536 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1), 539 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1), [all …]
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D | X86InstrSystem.td | 217 def STR16r : I<0x00, MRM1r, (outs GR16:$dst), (ins), 219 def STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins), 221 def STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins), 455 def RDGSBASE : I<0xAE, MRM1r, (outs GR32:$dst), (ins), 457 def RDGSBASE64 : RI<0xAE, MRM1r, (outs GR64:$dst), (ins),
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D | X86InstrArithmetic.td | 412 def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src1), 416 def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src1), 463 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1), 475 def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src1), "dec{q}\t$dst", 1089 defm OR : ArithBinOp_RF<0x08, 0x0A, 0x0C, "or", MRM1r, MRM1m,
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/external/llvm/lib/Target/X86/ |
D | X86InstrShiftRotate.td | 578 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1), 581 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src1), 584 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src1), 587 def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src1), 592 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2), 595 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2), 599 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2), 603 def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst), 610 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1), 614 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1), [all …]
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D | X86InstrSystem.td | 245 def STR16r : I<0x00, MRM1r, (outs GR16:$dst), (ins), 247 def STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins), 249 def STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins), 579 def RDGSBASE : I<0xAE, MRM1r, (outs GR32:$dst), (ins), 582 def RDGSBASE64 : RI<0xAE, MRM1r, (outs GR64:$dst), (ins),
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D | X86InstrFPStack.td | 279 def MUL_FST0r : FPST0rInst <MRM1r, "fmul\t$op">; 280 def MUL_FrST0 : FPrST0Inst <MRM1r, "fmul\t{%st(0), $op|$op, st(0)}">; 281 def MUL_FPrST0 : FPrST0PInst<MRM1r, "fmulp\t$op">; 387 def CMOVE_F : FPI<0xDA, MRM1r, (outs), (ins RST:$op), 395 def CMOVNE_F : FPI<0xDB, MRM1r, (outs), (ins RST:$op), 542 def XCH_F : FPI<0xD9, MRM1r, (outs), (ins RST:$op), "fxch\t$op", IIC_FXCH>;
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D | X86InstrArithmetic.td | 501 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1), 506 def DEC16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src1), 510 def DEC32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src1), 514 def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src1), "dec{q}\t$dst", 1193 defm OR : ArithBinOp_RF<0x08, 0x0A, 0x0C, "or", MRM1r, MRM1m,
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
D | X86InstrShiftRotate.td | 553 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1), 556 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src1), 559 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src1), 562 def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src1), 567 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2), 570 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2), 574 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2), 578 def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst), 584 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1), 587 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1), [all …]
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D | X86InstrSystem.td | 241 def STR16r : I<0x00, MRM1r, (outs GR16:$dst), (ins), 243 def STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins), 245 def STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins), 464 def RDSSPD : I<0x1E, MRM1r, (outs GR32:$dst), (ins GR32:$src), 467 def RDSSPQ : RI<0x1E, MRM1r, (outs GR64:$dst), (ins GR64:$src), 614 def RDGSBASE : I<0xAE, MRM1r, (outs GR32:$dst), (ins), 617 def RDGSBASE64 : RI<0xAE, MRM1r, (outs GR64:$dst), (ins),
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D | X86InstrFPStack.td | 286 def MUL_FST0r : FPST0rInst <MRM1r, "fmul\t$op">; 287 def MUL_FrST0 : FPrST0Inst <MRM1r, "fmul\t{%st(0), $op|$op, st(0)}">; 288 def MUL_FPrST0 : FPrST0PInst<MRM1r, "fmulp\t$op">; 405 def CMOVE_F : FPI<0xDA, MRM1r, (outs), (ins RST:$op), 413 def CMOVNE_F : FPI<0xDB, MRM1r, (outs), (ins RST:$op), 548 def XCH_F : FPI<0xD9, MRM1r, (outs), (ins RST:$op), "fxch\t$op">;
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D | X86InstrArithmetic.td | 475 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1), 479 def DEC16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src1), 482 def DEC32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src1), 485 def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src1), "dec{q}\t$dst", 1158 defm OR : ArithBinOp_RF<0x08, 0x0A, 0x0C, "or", MRM1r, MRM1m,
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/external/swiftshader/third_party/LLVM/utils/TableGen/ |
D | X86RecognizableInstr.cpp | 51 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, enumerator 728 case X86Local::MRM1r: in emitInstructionSpecifier() 820 case X86Local::MRM1r: in emitDecodePath() 909 case X86Local::MRM1r: in emitDecodePath()
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/external/llvm/lib/Target/X86/MCTargetDesc/ |
D | X86BaseInfo.h | 295 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 enumerator 685 case X86II::MRM0r: case X86II::MRM1r: in getMemoryOperandNo()
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D | X86MCCodeEmitter.cpp | 869 case X86II::MRM0r: case X86II::MRM1r: in EmitVEXOpcodePrefix() 1020 case X86II::MRM0r: case X86II::MRM1r: in DetermineREXPrefix() 1355 case X86II::MRM0r: case X86II::MRM1r: in encodeInstruction()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/MCTargetDesc/ |
D | X86BaseInfo.h | 343 MRM0r = 56, MRM1r = 57, MRM2r = 58, MRM3r = 59, // Format /0 /1 /2 /3 enumerator 727 case X86II::MRM0r: case X86II::MRM1r: in getMemoryOperandNo()
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D | X86MCCodeEmitter.cpp | 942 case X86II::MRM0r: case X86II::MRM1r: in EmitVEXOpcodePrefix() 1092 case X86II::MRM0r: case X86II::MRM1r: in DetermineREXPrefix() 1486 case X86II::MRM0r: case X86II::MRM1r: in encodeInstruction()
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/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
D | X86RecognizableInstr.h | 117 MRM0r = 56, MRM1r = 57, MRM2r = 58, MRM3r = 59, enumerator
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D | X86RecognizableInstr.cpp | 626 case X86Local::MRM1r: in emitInstructionSpecifier() 743 case X86Local::MRM0r: case X86Local::MRM1r: in emitDecodePath()
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D | X86FoldTablesEmitter.cpp | 416 (MemFormNum == X86Local::MRM1m && RegFormNum == X86Local::MRM1r) || in areOppositeForms()
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/external/llvm/utils/TableGen/ |
D | X86RecognizableInstr.cpp | 108 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, enumerator 716 case X86Local::MRM1r: in emitInstructionSpecifier() 852 case X86Local::MRM0r: case X86Local::MRM1r: in emitDecodePath()
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/external/llvm/test/TableGen/ |
D | TargetInstrInfo.td | 52 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
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/external/swiftshader/third_party/llvm-7.0/llvm/test/TableGen/ |
D | TargetInstrInfo.td | 52 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
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/external/swiftshader/third_party/LLVM/test/TableGen/ |
D | TargetInstrInfo.td | 52 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
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