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Searched refs:MRM5r (Results 1 – 25 of 34) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h216 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 enumerator
492 case X86II::MRM4r: case X86II::MRM5r: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp580 case X86II::MRM4r: case X86II::MRM5r: in EmitVEXOpcodePrefix()
966 case X86II::MRM4r: case X86II::MRM5r: in EncodeInstruction()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrShiftRotate.td111 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src1),
114 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
117 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
120 def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
125 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
128 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
131 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
134 def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
139 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
142 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
[all …]
DX86InstrArithmetic.td96 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
99 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
102 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
105 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src), "imul{q}\t$src", []>;
1095 defm SUB : ArithBinOp_RF<0x28, 0x2A, 0x2C, "sub", MRM5r, MRM5m,
DX86CodeEmitter.cpp903 case X86II::MRM4r: case X86II::MRM5r: in emitInstruction()
DX86InstrSystem.td330 def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
/external/llvm/lib/Target/X86/
DX86InstrShiftRotate.td126 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src1),
129 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
132 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
135 def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
140 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, u8imm:$src2),
143 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2),
147 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2),
151 def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, u8imm:$src2),
156 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
159 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
[all …]
DX86InstrFPStack.td271 def SUBR_FST0r : FPST0rInst <MRM5r, "fsubr\t$op">;
272 def SUB_FrST0 : FPrST0Inst <MRM5r, "fsub{r}\t{%st(0), $op|$op, st(0)}">;
273 def SUB_FPrST0 : FPrST0PInst<MRM5r, "fsub{r}p\t$op">;
591 def UCOM_FPr : FPI<0xDD, MRM5r, // FPSW = cmp ST(0) with ST(i), pop
598 def UCOM_FIr : FPI<0xDB, MRM5r, // CC = cmp ST(0) with ST(i)
600 def UCOM_FIPr : FPI<0xDF, MRM5r, // CC = cmp ST(0) with ST(i), pop
DX86InstrArithmetic.td113 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", [],
117 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", [],
121 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", [],
125 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src), "imul{q}\t$src", [],
1200 defm SUB : ArithBinOp_RF<0x28, 0x2A, 0x2C, "sub", MRM5r, MRM5m,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrShiftRotate.td124 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src1),
127 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
130 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
133 def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
138 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, u8imm:$src2),
141 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2),
145 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2),
149 def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, u8imm:$src2),
154 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
157 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
[all …]
DX86InstrFPStack.td274 def SUBR_FST0r : FPST0rInst <MRM5r, "fsubr\t$op">;
275 def SUB_FrST0 : FPrST0Inst <MRM5r, "fsub{r}\t{%st(0), $op|$op, st(0)}">;
276 def SUB_FPrST0 : FPrST0PInst<MRM5r, "fsub{r}p\t$op">;
606 def UCOM_FPr : FPI<0xDD, MRM5r, // FPSW = cmp ST(0) with ST(i), pop
613 def UCOM_FIr : FPI<0xDB, MRM5r, // CC = cmp ST(0) with ST(i)
615 def UCOM_FIPr : FPI<0xDF, MRM5r, // CC = cmp ST(0) with ST(i), pop
DX86InstrSystem.td350 def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg), "verw\t$seg", []>, TB, NotMemoryFoldable;
457 def INCSSPD : I<0xAE, MRM5r, (outs), (ins GR32:$src), "incsspd\t$src",
459 def INCSSPQ : RI<0xAE, MRM5r, (outs), (ins GR64:$src), "incsspq\t$src",
DX86InstrArithmetic.td112 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>,
116 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
120 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>,
124 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src), "imul{q}\t$src", []>,
1165 defm SUB : ArithBinOp_RF<0x28, 0x2A, 0x2C, "sub", MRM5r, MRM5m,
/external/swiftshader/third_party/LLVM/utils/TableGen/
DX86RecognizableInstr.cpp52 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, enumerator
732 case X86Local::MRM5r: in emitInstructionSpecifier()
824 case X86Local::MRM5r: in emitDecodePath()
913 case X86Local::MRM5r: in emitDecodePath()
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h296 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 enumerator
687 case X86II::MRM4r: case X86II::MRM5r: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp871 case X86II::MRM4r: case X86II::MRM5r: in EmitVEXOpcodePrefix()
1022 case X86II::MRM4r: case X86II::MRM5r: in DetermineREXPrefix()
1357 case X86II::MRM4r: case X86II::MRM5r: in encodeInstruction()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h344 MRM4r = 60, MRM5r = 61, MRM6r = 62, MRM7r = 63, // Format /4 /5 /6 /7 enumerator
729 case X86II::MRM4r: case X86II::MRM5r: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp944 case X86II::MRM4r: case X86II::MRM5r: in EmitVEXOpcodePrefix()
1094 case X86II::MRM4r: case X86II::MRM5r: in DetermineREXPrefix()
1488 case X86II::MRM4r: case X86II::MRM5r: in encodeInstruction()
/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DX86RecognizableInstr.h118 MRM4r = 60, MRM5r = 61, MRM6r = 62, MRM7r = 63, enumerator
DX86RecognizableInstr.cpp630 case X86Local::MRM5r: in emitInstructionSpecifier()
745 case X86Local::MRM4r: case X86Local::MRM5r: in emitDecodePath()
DX86FoldTablesEmitter.cpp420 (MemFormNum == X86Local::MRM5m && RegFormNum == X86Local::MRM5r) || in areOppositeForms()
/external/llvm/utils/TableGen/
DX86RecognizableInstr.cpp109 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, enumerator
720 case X86Local::MRM5r: in emitInstructionSpecifier()
854 case X86Local::MRM4r: case X86Local::MRM5r: in emitDecodePath()
/external/llvm/test/TableGen/
DTargetInstrInfo.td53 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
/external/swiftshader/third_party/llvm-7.0/llvm/test/TableGen/
DTargetInstrInfo.td53 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
/external/swiftshader/third_party/LLVM/test/TableGen/
DTargetInstrInfo.td53 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;

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