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Searched refs:MSR_DR (Results 1 – 10 of 10) sorted by relevance

/external/python/cpython2/Lib/plat-aix3/
DIN.py24 MSR_DR = 0x0010 variable
26 DEFAULT_MSR = (MSR_EE | MSR_ME | MSR_AL | MSR_IR | MSR_DR)
/external/python/cpython2/Lib/plat-aix4/
DIN.py24 MSR_DR = 0x0010 variable
26 DEFAULT_MSR = (MSR_EE | MSR_ME | MSR_AL | MSR_IR | MSR_DR)
/external/u-boot/arch/powerpc/cpu/mpc83xx/
Dcpu.c135 msr &= ~( MSR_EE | MSR_IR | MSR_DR); in do_reset()
158 msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR); in do_reset()
Dtraps.c61 regs->msr&MSR_DR ? 1 : 0); in show_regs()
Dstart.S101 ori r5, r5, (MSR_IR | MSR_DR)
111 andi. r0, r3, (MSR_IR | MSR_DR)
/external/u-boot/arch/powerpc/cpu/mpc8xx/
Dtraps.c64 regs->msr & MSR_DR ? 1 : 0); in show_regs()
/external/u-boot/arch/powerpc/cpu/mpc86xx/
Dtraps.c70 regs->msr & MSR_DR ? 1 : 0); in show_regs()
Dstart.S198 ori r5, r5, (MSR_IR | MSR_DR)
371 ori r3, r3, (MSR_IR | MSR_DR)
477 andi. r0, r3, (MSR_IR | MSR_DR)
/external/u-boot/arch/powerpc/cpu/mpc85xx/
Dtraps.c97 regs->msr&MSR_DR ? 1 : 0); in show_regs()
/external/u-boot/arch/powerpc/include/asm/
Dprocessor.h41 #define MSR_DR (1<<4) /* Data Relocate */ macro
55 #define MSR_KERNEL MSR_|MSR_IR|MSR_DR