| /external/v8/src/compiler/mips/ |
| D | instruction-scheduler-mips.cc | 333 MSUB_S = 4, enumerator
619 return Latency::MSUB_S; in MsubSLatency()
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| /external/v8/src/compiler/mips64/ |
| D | instruction-scheduler-mips64.cc | 366 MSUB_S = 4, enumerator
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| /external/v8/src/mips/ |
| D | constants-mips.h | 717 MSUB_S = ((5U << 3) + 0), enumerator
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| D | disasm-mips.cc | 1627 case MSUB_S: in DecodeTypeRegister()
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| D | assembler-mips.cc | 2789 GenInstrRegister(COP1X, fr, ft, fs, fd, MSUB_S); in msub_s()
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| D | simulator-mips.cc | 3745 case MSUB_S: { in DecodeTypeRegisterCOP1X()
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| /external/v8/src/mips64/ |
| D | constants-mips64.h | 748 MSUB_S = ((5U << 3) + 0), enumerator
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| D | disasm-mips64.cc | 1414 case MSUB_S: in DecodeTypeRegisterCOP1X()
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| D | simulator-mips64.cc | 3620 case MSUB_S: { in DecodeTypeRegisterCOP1X()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsScheduleP5600.td | 489 (instrs MADD_D32, MADD_D64, MADD_S, MSUB_D32, MSUB_D64, MSUB_S,
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| D | MipsInstrFPU.td | 621 def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>,
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| /external/llvm/lib/Target/Mips/ |
| D | MipsInstrFPU.td | 483 def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>,
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenSubtargetInfo.inc | 927 {DBGFIELD("MSUB_S") 1, false, false, 15, 2, 6, 1, 0, 0}, // #652
1947 {DBGFIELD("MSUB_S") 1, false, false, 58, 2, 13, 1, 1, 1}, // #652
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| D | MipsGenMCCodeEmitter.inc | 1949 UINT64_C(1275068456), // MSUB_S
3122 case Mips::MSUB_S:
9675 …Mips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | Feature_HasMadd4 | 0, // MSUB_S = 1936
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| D | MipsGenInstrInfo.inc | 1951 MSUB_S = 1936,
3309 MSUB_S = 652,
5996 …, 4, 1, 4, 652, 0, 0x4ULL, nullptr, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #1936 = MSUB_S
10195 { Mips::MSUB_S, Mips::MSUB_S, Mips::MSUB_S_MM },
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| D | MipsGenAsmWriter.inc | 3164 268458766U, // MSUB_S
5795 4672U, // MSUB_S
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| D | MipsGenGlobalISel.inc | 13988 …f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr) => (MSUB_S:{ *:[f32] } FGR32O…
13989 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUB_S,
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| D | MipsGenDisassemblerTables.inc | 3671 /* 4556 */ MCD::OPC_Decode, 144, 15, 227, 1, // Opcode: MSUB_S
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| D | MipsGenAsmMatcher.inc | 6749 …{ 6553 /* msub.s */, Mips::MSUB_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32A…
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| D | MipsGenDAGISel.inc | 27300 /* 51314*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MSUB_S), 0,
27303 …// Dst: (MSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f…
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| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 1169 33576977U, // MSUB_S
2883 5U, // MSUB_S
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| D | MipsGenDisassemblerTables.inc | 1227 /* 3412 */ MCD_OPC_Decode, 128, 9, 91, // Opcode: MSUB_S
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