Searched refs:MTHC1 (Results 1 – 12 of 12) sorted by relevance
/external/llvm/test/CodeGen/Mips/llvm-ir/ |
D | ret.ll | 10 …=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,NO-MTHC1,NOT-R6 11 …rch=mips -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,NOT-R6 12 …rch=mips -mcpu=mips32r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,NOT-R6 13 …rch=mips -mcpu=mips32r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,NOT-R6 14 …-march=mips -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,R6C 162 ; NO-MTHC1-DAG: mtc1 $zero, $f0 164 ; MTHC1-DAG: mtc1 $zero, $f0 192 ; NO-MTHC1-DAG: mtc1 $zero, $f0 193 ; NO-MTHC1-DAG: mtc1 $zero, $f1 195 ; MTHC1-DAG: mtc1 $zero, $f0 [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/llvm-ir/ |
D | ret.ll | 10 …=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,NO-MTHC1,NOT-R6 11 …rch=mips -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,NOT-R6 12 …rch=mips -mcpu=mips32r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,NOT-R6 13 …rch=mips -mcpu=mips32r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,NOT-R6 14 …-march=mips -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,R6C 162 ; NO-MTHC1-DAG: mtc1 $zero, $f0 164 ; MTHC1-DAG: mtc1 $zero, $f0 192 ; NO-MTHC1-DAG: mtc1 $zero, $f0 193 ; NO-MTHC1-DAG: mtc1 $zero, $f1 195 ; MTHC1-DAG: mtc1 $zero, $f0 [all …]
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/external/v8/src/compiler/mips64/ |
D | instruction-scheduler-mips64.cc | 442 MTHC1 = 4, enumerator 1035 Latency::MTHC1; in Float64RoundLatency() 1529 Latency::MTC1 + Latency::MFC1 + Latency::MTHC1 + 1; in GetInstructionLatency() 1546 return Latency::MFHC1 + Latency::MTC1 + Latency::MTHC1; in GetInstructionLatency() 1550 return Latency::MTHC1; in GetInstructionLatency()
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/external/v8/src/compiler/mips/ |
D | instruction-scheduler-mips.cc | 409 MTHC1 = 4, enumerator 759 return Latency::MFHC1 + Latency::MTC1 + Latency::MTHC1; in FmoveLowLatency() 1535 return Latency::MFHC1 + Latency::MTC1 + Latency::MTHC1; in GetInstructionLatency()
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/external/v8/src/mips/ |
D | constants-mips.h | 591 MTHC1 = ((0U << 3) + 7) << 21, enumerator
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D | disasm-mips.cc | 1597 case MTHC1: in DecodeTypeRegister()
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D | assembler-mips.cc | 2606 GenInstrRegister(COP1, MTHC1, rt, fs, f0); in mthc1()
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D | simulator-mips.cc | 3699 case MTHC1: in DecodeTypeRegisterCOP1()
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/external/v8/src/mips64/ |
D | constants-mips64.h | 622 MTHC1 = ((0U << 3) + 7) << 21, enumerator
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D | disasm-mips64.cc | 1385 case MTHC1: in DecodeTypeRegisterCOP1()
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D | assembler-mips64.cc | 2993 GenInstrRegister(COP1, MTHC1, rt, fs, f0); in mthc1()
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D | simulator-mips64.cc | 3587 case MTHC1: in DecodeTypeRegisterCOP1()
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