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Searched refs:MTRR_PHYS_BASE_MSR (Results 1 – 6 of 6) sorted by relevance

/external/u-boot/arch/x86/cpu/intel_common/
Dcar.S21 #define MTRR_PHYS_BASE_MSR(reg) (0x200 + 2 * (reg)) macro
81 movl $(MTRR_PHYS_BASE_MSR(0)), %ecx
134 movl $MTRR_PHYS_BASE_MSR(1), %ecx
149 movl $MTRR_PHYS_BASE_MSR(2), %ecx
206 movl $MTRR_PHYS_BASE_MSR(2), %ecx
/external/u-boot/arch/x86/cpu/coreboot/
Dcoreboot.c51 u8 top_type = native_read_msr(MTRR_PHYS_BASE_MSR(top_mtrr)) & 0xff; in board_final_cleanup()
58 wrmsrl(MTRR_PHYS_BASE_MSR(top_mtrr), 0); in board_final_cleanup()
/external/u-boot/cmd/x86/
Dmtrr.c31 base = native_read_msr(MTRR_PHYS_BASE_MSR(i)); in do_mtrr_list()
77 wrmsrl(MTRR_PHYS_BASE_MSR(reg), base); in do_mtrr_set()
/external/u-boot/arch/x86/include/asm/
Dmtrr.h31 #define MTRR_PHYS_BASE_MSR(reg) (0x200 + 2 * (reg)) macro
/external/u-boot/arch/x86/cpu/
Dmtrr.c60 wrmsrl(MTRR_PHYS_BASE_MSR(i), req->start | req->type); in mtrr_commit()
Dmp_init.c207 msr_entry = save_msr(MTRR_PHYS_BASE_MSR(i), msr_entry); in save_bsp_msrs()