| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
| D | mubuf.ll | 6 ;;; MUBUF LOAD TESTS
9 ; MUBUF load with an immediate byte offset that fits into 12-bits
20 ; MUBUF load with the largest possible immediate offset
31 ; MUBUF load with an immediate byte offset that doesn't fit into 12-bits
43 ; MUBUF load with a 12-bit immediate offset and a register offset
90 ;;; MUBUF STORE TESTS
93 ; MUBUF store with an immediate byte offset that fits into 12-bits
103 ; MUBUF store with the largest possible immediate offset
114 ; MUBUF store with an immediate byte offset that doesn't fit into 12-bits
125 ; MUBUF store with a 12-bit immediate offset and a register offset
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| D | schedule-global-loads.ll | 23 ; an MUBUF load which does not have a vaddr operand.
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| D | local-stack-slot-offset.ll | 6 ; MUBUF instructions, so a new base register is needed. This used to not
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| D | mubuf-offset-private.ll | 136 ; MUBUF used for stack access has bounds checking enabled before gfx9,
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| D | concat_vectors.ll | 5 ; 0x80f000 is the high 32 bits of the resource descriptor used by MUBUF
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| /external/llvm/test/CodeGen/AMDGPU/ |
| D | mubuf.ll | 6 ;;; MUBUF LOAD TESTS
9 ; MUBUF load with an immediate byte offset that fits into 12-bits
20 ; MUBUF load with the largest possible immediate offset
31 ; MUBUF load with an immediate byte offset that doesn't fit into 12-bits
43 ; MUBUF load with a 12-bit immediate offset and a register offset
88 ;;; MUBUF STORE TESTS
91 ; MUBUF store with an immediate byte offset that fits into 12-bits
101 ; MUBUF store with the largest possible immediate offset
112 ; MUBUF store with an immediate byte offset that doesn't fit into 12-bits
123 ; MUBUF store with a 12-bit immediate offset and a register offset
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| D | schedule-global-loads.ll | 24 ; an MUBUF load which does not have a vaddr operand.
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| D | concat_vectors.ll | 5 ; 0x80f000 is the high 32 bits of the resource descriptor used by MUBUF
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| /external/llvm/docs/ |
| D | AMDGPUUsage.rst | 55 MUBUF Instructions
57 All non-atomic MUBUF instructions are supported.
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstructions.td | 928 // MUBUF Instructions
2159 (!cast<MUBUF>(opcode # _OFFSET) $rsrc, $soffset, (as_i16imm $offset),
2167 (!cast<MUBUF>(opcode # _IDXEN) $vindex, $rsrc, $soffset, (as_i16imm $offset),
2175 (!cast<MUBUF>(opcode # _OFFEN) $voffset, $rsrc, $soffset, (as_i16imm $offset),
2183 (!cast<MUBUF>(opcode # _BOTHEN)
2203 (!cast<MUBUF>(opcode # _OFFSET) $vdata, $rsrc, $soffset, (as_i16imm $offset),
2211 (!cast<MUBUF>(opcode # _IDXEN) $vdata, $vindex, $rsrc, $soffset,
2220 (!cast<MUBUF>(opcode # _OFFEN) $vdata, $voffset, $rsrc, $soffset,
2229 (!cast<MUBUF>(opcode # _BOTHEN)
2252 (!cast<MUBUF>(opcode # _RTN_OFFSET) $vdata_in, $rsrc, $soffset,
[all …]
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| D | SIInstrFormats.td | 38 field bits<1> MUBUF = 0;
74 let TSFlags{16} = MUBUF;
686 class MUBUF <dag outs, dag ins, string asm, list<dag> pattern> :
691 let MUBUF = 1;
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| D | SIDefines.h | 35 MUBUF = 1 << 16, enumerator
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| D | SIInstrInfo.h | 280 return MI.getDesc().TSFlags & SIInstrFlags::MUBUF; in isMUBUF()
284 return get(Opcode).TSFlags & SIInstrFlags::MUBUF; in isMUBUF()
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| D | CIInstructions.td | 100 // MUBUF Instructions
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| D | SIInstrInfo.td | 2881 // MUBUF classes
2892 MUBUF <outs, ins, asm, pattern>, MUBUFe <op> {
2899 MUBUF <outs, ins, asm, pattern>, MUBUFe_vi <op> {
2909 MUBUF <outs, ins, "", pattern>,
2926 MUBUF <outs, ins, asm, []>,
2937 MUBUF <outs, ins, asm, []>,
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrFormats.td | 49 field bit MUBUF = 0;
144 let TSFlags{16} = MUBUF;
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| D | SIDefines.h | 46 MUBUF = 1 << 16, enumerator
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| D | SIInstrInfo.h | 405 return MI.getDesc().TSFlags & SIInstrFlags::MUBUF; in isMUBUF()
409 return get(Opcode).TSFlags & SIInstrFlags::MUBUF; in isMUBUF()
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| D | AMDGPU.td | 369 // to missing ADDR64 variants of MUBUF instructions.
370 // FIXME: moveToVALU should be able to handle converting addr64 MUBUF
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| D | BUFInstructions.td | 290 // MUBUF classes
308 let MUBUF = 1;
695 // MUBUF Instructions
1030 // MUBUF Patterns
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| D | SMInstructions.td | 419 // Global and constant loads can be selected to either MUBUF or SMRD
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| /external/swiftshader/third_party/llvm-7.0/llvm/docs/ |
| D | AMDGPUOperandSyntax.rst | 430 MUBUF/MTBUF Modifiers
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| D | AMDGPUUsage.rst | 4159 MUBUF subsubsection
4170 For full list of supported instructions, refer to "MUBUF Instructions" in ISA Manual.
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| D | AMDGPUAsmGFX7.rst | 289 MUBUF chapter
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| D | AMDGPUAsmGFX8.rst | 286 MUBUF chapter
|