Searched refs:MUSB_CSR0_TXPKTRDY (Results 1 – 7 of 7) sorted by relevance
132 case MUSB_CSR0_TXPKTRDY: in wait_until_ep0_ready()133 if (!(csr & MUSB_CSR0_TXPKTRDY)) { in wait_until_ep0_ready()252 csr |= (MUSB_CSR0_TXPKTRDY|MUSB_CSR0_H_SETUPPKT); in ctrlreq_setup_phase()256 result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY); in ctrlreq_setup_phase()329 csr |= MUSB_CSR0_TXPKTRDY; in ctrlreq_out_data_phase()334 result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY); in ctrlreq_out_data_phase()354 csr |= (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_H_STATUSPKT); in ctrlreq_out_status_phase()361 result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY); in ctrlreq_out_status_phase()
232 csr0 |= MUSB_CSR0_TXPKTRDY; in musb_ep0_tx_ready()241 csr0 |= (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_P_DATAEND); in musb_ep0_tx_ready_and_last()541 if (csr0 & MUSB_CSR0_TXPKTRDY) in musb_peri_ep0_tx()579 if (!(csr0 & MUSB_CSR0_TXPKTRDY)) in musb_peri_ep0_tx()
178 #define MUSB_CSR0_TXPKTRDY 0x0002 macro
526 u16 csr = MUSB_CSR0_TXPKTRDY; in ep0_txstate()613 musb->ackpend |= MUSB_CSR0_TXPKTRDY; in musb_read_setup()707 if ((csr & MUSB_CSR0_TXPKTRDY) == 0) { in musb_g_ep0_irq()836 musb->ackpend = MUSB_CSR0_TXPKTRDY in musb_g_ep0_irq()
75 #define MUSB_CSR0_TXPKTRDY 0x0002 macro
122 if (!(csr & (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_RXPKTRDY))) in musb_h_ep0_flush_fifo()150 txcsr = MUSB_CSR0_H_SETUPPKT | MUSB_CSR0_TXPKTRDY; in musb_h_tx_start()1055 ? MUSB_CSR0_H_REQPKT : MUSB_CSR0_TXPKTRDY; in musb_h_ep0_irq()1064 | MUSB_CSR0_TXPKTRDY; in musb_h_ep0_irq()
327 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY); in musb_load_testpacket()