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1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2009
4  * Marvell Semiconductor <www.marvell.com>
5  * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
6  *
7  * based on - Driver for MV64360X ethernet ports
8  * Copyright (C) 2002 rabeeh@galileo.co.il
9  */
10 
11 #ifndef __MVGBE_H__
12 #define __MVGBE_H__
13 
14 /* PHY_BASE_ADR is board specific and can be configured */
15 #if defined (CONFIG_PHY_BASE_ADR)
16 #define PHY_BASE_ADR		CONFIG_PHY_BASE_ADR
17 #else
18 #define PHY_BASE_ADR		0x08	/* default phy base addr */
19 #endif
20 
21 /* Constants */
22 #define INT_CAUSE_UNMASK_ALL		0x0007ffff
23 #define INT_CAUSE_UNMASK_ALL_EXT	0x0011ffff
24 #define MRU_MASK			0xfff1ffff
25 #define PHYADR_MASK			0x0000001f
26 #define PHYREG_MASK			0x0000001f
27 #define QTKNBKT_DEF_VAL			0x3fffffff
28 #define QMTBS_DEF_VAL			0x000003ff
29 #define QTKNRT_DEF_VAL			0x0000fcff
30 #define RXUQ	0 /* Used Rx queue */
31 #define TXUQ	0 /* Used Rx queue */
32 
33 #define to_mvgbe(_d) container_of(_d, struct mvgbe_device, dev)
34 #define MVGBE_REG_WR(adr, val)		writel(val, &adr)
35 #define MVGBE_REG_RD(adr)		readl(&adr)
36 #define MVGBE_REG_BITS_RESET(adr, val)	writel(readl(&adr) & ~(val), &adr)
37 #define MVGBE_REG_BITS_SET(adr, val)	writel(readl(&adr) | val, &adr)
38 
39 /* Default port configuration value */
40 #define PRT_CFG_VAL			( \
41 	MVGBE_UCAST_MOD_NRML		| \
42 	MVGBE_DFLT_RXQ(RXUQ)		| \
43 	MVGBE_DFLT_RX_ARPQ(RXUQ)	| \
44 	MVGBE_RX_BC_IF_NOT_IP_OR_ARP	| \
45 	MVGBE_RX_BC_IF_IP		| \
46 	MVGBE_RX_BC_IF_ARP		| \
47 	MVGBE_CPTR_TCP_FRMS_DIS		| \
48 	MVGBE_CPTR_UDP_FRMS_DIS		| \
49 	MVGBE_DFLT_RX_TCPQ(RXUQ)	| \
50 	MVGBE_DFLT_RX_UDPQ(RXUQ)	| \
51 	MVGBE_DFLT_RX_BPDUQ(RXUQ))
52 
53 /* Default port extend configuration value */
54 #define PORT_CFG_EXTEND_VALUE		\
55 	MVGBE_SPAN_BPDU_PACKETS_AS_NORMAL	| \
56 	MVGBE_PARTITION_DIS		| \
57 	MVGBE_TX_CRC_GENERATION_EN
58 
59 #define GT_MVGBE_IPG_INT_RX(value)	((value & 0x3fff) << 8)
60 
61 /* Default sdma control value */
62 #define PORT_SDMA_CFG_VALUE		( \
63 	MVGBE_RX_BURST_SIZE_16_64BIT	| \
64 	MVGBE_BLM_RX_NO_SWAP		| \
65 	MVGBE_BLM_TX_NO_SWAP		| \
66 	GT_MVGBE_IPG_INT_RX(RXUQ)	| \
67 	MVGBE_TX_BURST_SIZE_16_64BIT)
68 
69 /* Default port serial control value */
70 #ifndef PORT_SERIAL_CONTROL_VALUE
71 #define PORT_SERIAL_CONTROL_VALUE		( \
72 	MVGBE_FORCE_LINK_PASS			| \
73 	MVGBE_DIS_AUTO_NEG_FOR_DUPLX		| \
74 	MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL	| \
75 	MVGBE_ADV_NO_FLOW_CTRL			| \
76 	MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX	| \
77 	MVGBE_FORCE_BP_MODE_NO_JAM		| \
78 	(1 << 9) /* Reserved bit has to be 1 */	| \
79 	MVGBE_DO_NOT_FORCE_LINK_FAIL		| \
80 	MVGBE_EN_AUTO_NEG_SPEED_GMII		| \
81 	MVGBE_DTE_ADV_0				| \
82 	MVGBE_MIIPHY_MAC_MODE			| \
83 	MVGBE_AUTO_NEG_NO_CHANGE		| \
84 	MVGBE_MAX_RX_PACKET_1552BYTE		| \
85 	MVGBE_CLR_EXT_LOOPBACK			| \
86 	MVGBE_SET_FULL_DUPLEX_MODE		| \
87 	MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX)
88 #endif
89 
90 /* Tx WRR confoguration macros */
91 #define PORT_MAX_TRAN_UNIT	0x24	/* MTU register (default) 9KByte */
92 #define PORT_MAX_TOKEN_BUCKET_SIZE	0x_FFFF	/* PMTBS reg (default) */
93 #define PORT_TOKEN_RATE		1023	/* PTTBRC reg (default) */
94 /* MAC accepet/reject macros */
95 #define ACCEPT_MAC_ADDR		0
96 #define REJECT_MAC_ADDR		1
97 /* Size of a Tx/Rx descriptor used in chain list data structure */
98 #define MV_RXQ_DESC_ALIGNED_SIZE	\
99 	(((sizeof(struct mvgbe_rxdesc) / PKTALIGN) + 1) * PKTALIGN)
100 /* Buffer offset from buffer pointer */
101 #define RX_BUF_OFFSET		0x2
102 
103 /* Port serial status reg (PSR) */
104 #define MVGBE_INTERFACE_GMII_MII	0
105 #define MVGBE_INTERFACE_PCM		1
106 #define MVGBE_LINK_IS_DOWN		0
107 #define MVGBE_LINK_IS_UP		(1 << 1)
108 #define MVGBE_PORT_AT_HALF_DUPLEX	0
109 #define MVGBE_PORT_AT_FULL_DUPLEX	(1 << 2)
110 #define MVGBE_RX_FLOW_CTRL_DISD		0
111 #define MVGBE_RX_FLOW_CTRL_ENBALED	(1 << 3)
112 #define MVGBE_GMII_SPEED_100_10		0
113 #define MVGBE_GMII_SPEED_1000		(1 << 4)
114 #define MVGBE_MII_SPEED_10		0
115 #define MVGBE_MII_SPEED_100		(1 << 5)
116 #define MVGBE_NO_TX			0
117 #define MVGBE_TX_IN_PROGRESS		(1 << 7)
118 #define MVGBE_BYPASS_NO_ACTIVE		0
119 #define MVGBE_BYPASS_ACTIVE		(1 << 8)
120 #define MVGBE_PORT_NOT_AT_PARTN_STT	0
121 #define MVGBE_PORT_AT_PARTN_STT		(1 << 9)
122 #define MVGBE_PORT_TX_FIFO_NOT_EMPTY	0
123 #define MVGBE_PORT_TX_FIFO_EMPTY	(1 << 10)
124 
125 /* These macros describes the Port configuration reg (Px_cR) bits */
126 #define MVGBE_UCAST_MOD_NRML		0
127 #define MVGBE_UNICAST_PROMISCUOUS_MODE	1
128 #define MVGBE_DFLT_RXQ(_x)		(_x << 1)
129 #define MVGBE_DFLT_RX_ARPQ(_x)		(_x << 4)
130 #define MVGBE_RX_BC_IF_NOT_IP_OR_ARP	0
131 #define MVGBE_REJECT_BC_IF_NOT_IP_OR_ARP (1 << 7)
132 #define MVGBE_RX_BC_IF_IP		0
133 #define MVGBE_REJECT_BC_IF_IP		(1 << 8)
134 #define MVGBE_RX_BC_IF_ARP		0
135 #define MVGBE_REJECT_BC_IF_ARP		(1 << 9)
136 #define MVGBE_TX_AM_NO_UPDATE_ERR_SMRY	(1 << 12)
137 #define MVGBE_CPTR_TCP_FRMS_DIS		0
138 #define MVGBE_CPTR_TCP_FRMS_EN		(1 << 14)
139 #define MVGBE_CPTR_UDP_FRMS_DIS		0
140 #define MVGBE_CPTR_UDP_FRMS_EN		(1 << 15)
141 #define MVGBE_DFLT_RX_TCPQ(_x)		(_x << 16)
142 #define MVGBE_DFLT_RX_UDPQ(_x)		(_x << 19)
143 #define MVGBE_DFLT_RX_BPDUQ(_x)		(_x << 22)
144 #define MVGBE_DFLT_RX_TCP_CHKSUM_MODE	(1 << 25)
145 
146 /* These macros describes the Port configuration extend reg (Px_cXR) bits*/
147 #define MVGBE_CLASSIFY_EN			1
148 #define MVGBE_SPAN_BPDU_PACKETS_AS_NORMAL	0
149 #define MVGBE_SPAN_BPDU_PACKETS_TO_RX_Q7	(1 << 1)
150 #define MVGBE_PARTITION_DIS			0
151 #define MVGBE_PARTITION_EN			(1 << 2)
152 #define MVGBE_TX_CRC_GENERATION_EN		0
153 #define MVGBE_TX_CRC_GENERATION_DIS		(1 << 3)
154 
155 /* These macros describes the Port Sdma configuration reg (SDCR) bits */
156 #define MVGBE_RIFB				1
157 #define MVGBE_RX_BURST_SIZE_1_64BIT		0
158 #define MVGBE_RX_BURST_SIZE_2_64BIT		(1 << 1)
159 #define MVGBE_RX_BURST_SIZE_4_64BIT		(1 << 2)
160 #define MVGBE_RX_BURST_SIZE_8_64BIT		((1 << 2) | (1 << 1))
161 #define MVGBE_RX_BURST_SIZE_16_64BIT		(1 << 3)
162 #define MVGBE_BLM_RX_NO_SWAP			(1 << 4)
163 #define MVGBE_BLM_RX_BYTE_SWAP			0
164 #define MVGBE_BLM_TX_NO_SWAP			(1 << 5)
165 #define MVGBE_BLM_TX_BYTE_SWAP			0
166 #define MVGBE_DESCRIPTORS_BYTE_SWAP		(1 << 6)
167 #define MVGBE_DESCRIPTORS_NO_SWAP		0
168 #define MVGBE_TX_BURST_SIZE_1_64BIT		0
169 #define MVGBE_TX_BURST_SIZE_2_64BIT		(1 << 22)
170 #define MVGBE_TX_BURST_SIZE_4_64BIT		(1 << 23)
171 #define MVGBE_TX_BURST_SIZE_8_64BIT		((1 << 23) | (1 << 22))
172 #define MVGBE_TX_BURST_SIZE_16_64BIT		(1 << 24)
173 
174 /* These macros describes the Port serial control reg (PSCR) bits */
175 #define MVGBE_SERIAL_PORT_DIS			0
176 #define MVGBE_SERIAL_PORT_EN			1
177 #define MVGBE_FORCE_LINK_PASS			(1 << 1)
178 #define MVGBE_DO_NOT_FORCE_LINK_PASS		0
179 #define MVGBE_EN_AUTO_NEG_FOR_DUPLX		0
180 #define MVGBE_DIS_AUTO_NEG_FOR_DUPLX		(1 << 2)
181 #define MVGBE_EN_AUTO_NEG_FOR_FLOW_CTRL		0
182 #define MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL	(1 << 3)
183 #define MVGBE_ADV_NO_FLOW_CTRL			0
184 #define MVGBE_ADV_SYMMETRIC_FLOW_CTRL		(1 << 4)
185 #define MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX	0
186 #define MVGBE_FORCE_FC_MODE_TX_PAUSE_DIS	(1 << 5)
187 #define MVGBE_FORCE_BP_MODE_NO_JAM		0
188 #define MVGBE_FORCE_BP_MODE_JAM_TX		(1 << 7)
189 #define MVGBE_FORCE_BP_MODE_JAM_TX_ON_RX_ERR	(1 << 8)
190 #define MVGBE_FORCE_LINK_FAIL			0
191 #define MVGBE_DO_NOT_FORCE_LINK_FAIL		(1 << 10)
192 #define MVGBE_DIS_AUTO_NEG_SPEED_GMII		(1 << 13)
193 #define MVGBE_EN_AUTO_NEG_SPEED_GMII		0
194 #define MVGBE_DTE_ADV_0				0
195 #define MVGBE_DTE_ADV_1				(1 << 14)
196 #define MVGBE_MIIPHY_MAC_MODE			0
197 #define MVGBE_MIIPHY_PHY_MODE			(1 << 15)
198 #define MVGBE_AUTO_NEG_NO_CHANGE		0
199 #define MVGBE_RESTART_AUTO_NEG			(1 << 16)
200 #define MVGBE_MAX_RX_PACKET_1518BYTE		0
201 #define MVGBE_MAX_RX_PACKET_1522BYTE		(1 << 17)
202 #define MVGBE_MAX_RX_PACKET_1552BYTE		(1 << 18)
203 #define MVGBE_MAX_RX_PACKET_9022BYTE		((1 << 18) | (1 << 17))
204 #define MVGBE_MAX_RX_PACKET_9192BYTE		(1 << 19)
205 #define MVGBE_MAX_RX_PACKET_9700BYTE		((1 << 19) | (1 << 17))
206 #define MVGBE_SET_EXT_LOOPBACK			(1 << 20)
207 #define MVGBE_CLR_EXT_LOOPBACK			0
208 #define MVGBE_SET_FULL_DUPLEX_MODE		(1 << 21)
209 #define MVGBE_SET_HALF_DUPLEX_MODE		0
210 #define MVGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	(1 << 22)
211 #define MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
212 #define MVGBE_SET_GMII_SPEED_TO_10_100		0
213 #define MVGBE_SET_GMII_SPEED_TO_1000		(1 << 23)
214 #define MVGBE_SET_MII_SPEED_TO_10		0
215 #define MVGBE_SET_MII_SPEED_TO_100		(1 << 24)
216 
217 /* SMI register fields */
218 #define MVGBE_PHY_SMI_TIMEOUT		10000
219 #define MVGBE_PHY_SMI_TIMEOUT_MS	1000
220 #define MVGBE_PHY_SMI_DATA_OFFS		0	/* Data */
221 #define MVGBE_PHY_SMI_DATA_MASK		(0xffff << MVGBE_PHY_SMI_DATA_OFFS)
222 #define MVGBE_PHY_SMI_DEV_ADDR_OFFS	16	/* PHY device address */
223 #define MVGBE_PHY_SMI_DEV_ADDR_MASK \
224 	(PHYADR_MASK << MVGBE_PHY_SMI_DEV_ADDR_OFFS)
225 #define MVGBE_SMI_REG_ADDR_OFFS		21	/* PHY device reg addr */
226 #define MVGBE_SMI_REG_ADDR_MASK \
227 	(PHYADR_MASK << MVGBE_SMI_REG_ADDR_OFFS)
228 #define MVGBE_PHY_SMI_OPCODE_OFFS	26	/* Write/Read opcode */
229 #define MVGBE_PHY_SMI_OPCODE_MASK	(3 << MVGBE_PHY_SMI_OPCODE_OFFS)
230 #define MVGBE_PHY_SMI_OPCODE_WRITE	(0 << MVGBE_PHY_SMI_OPCODE_OFFS)
231 #define MVGBE_PHY_SMI_OPCODE_READ	(1 << MVGBE_PHY_SMI_OPCODE_OFFS)
232 #define MVGBE_PHY_SMI_READ_VALID_MASK	(1 << 27)	/* Read Valid */
233 #define MVGBE_PHY_SMI_BUSY_MASK		(1 << 28)	/* Busy */
234 
235 /* SDMA command status fields macros */
236 /* Tx & Rx descriptors status */
237 #define MVGBE_ERROR_SUMMARY		1
238 /* Tx & Rx descriptors command */
239 #define MVGBE_BUFFER_OWNED_BY_DMA	(1 << 31)
240 /* Tx descriptors status */
241 #define MVGBE_LC_ERROR			0
242 #define MVGBE_UR_ERROR			(1 << 1)
243 #define MVGBE_RL_ERROR			(1 << 2)
244 #define MVGBE_LLC_SNAP_FORMAT		(1 << 9)
245 #define MVGBE_TX_LAST_FRAME		(1 << 20)
246 
247 /* Rx descriptors status */
248 #define MVGBE_CRC_ERROR			0
249 #define MVGBE_OVERRUN_ERROR		(1 << 1)
250 #define MVGBE_MAX_FRAME_LENGTH_ERROR	(1 << 2)
251 #define MVGBE_RESOURCE_ERROR		((1 << 2) | (1 << 1))
252 #define MVGBE_VLAN_TAGGED		(1 << 19)
253 #define MVGBE_BPDU_FRAME		(1 << 20)
254 #define MVGBE_TCP_FRAME_OVER_IP_V_4	0
255 #define MVGBE_UDP_FRAME_OVER_IP_V_4	(1 << 21)
256 #define MVGBE_OTHER_FRAME_TYPE		(1 << 22)
257 #define MVGBE_LAYER_2_IS_MVGBE_V_2	(1 << 23)
258 #define MVGBE_FRAME_TYPE_IP_V_4		(1 << 24)
259 #define MVGBE_FRAME_HEADER_OK		(1 << 25)
260 #define MVGBE_RX_LAST_DESC		(1 << 26)
261 #define MVGBE_RX_FIRST_DESC		(1 << 27)
262 #define MVGBE_UNKNOWN_DESTINATION_ADDR	(1 << 28)
263 #define MVGBE_RX_EN_INTERRUPT		(1 << 29)
264 #define MVGBE_LAYER_4_CHECKSUM_OK	(1 << 30)
265 
266 /* Rx descriptors byte count */
267 #define MVGBE_FRAME_FRAGMENTED		(1 << 2)
268 
269 /* Tx descriptors command */
270 #define MVGBE_LAYER_4_CHECKSUM_FIRST_DESC	(1 << 10)
271 #define MVGBE_FRAME_SET_TO_VLAN			(1 << 15)
272 #define MVGBE_TCP_FRAME				0
273 #define MVGBE_UDP_FRAME				(1 << 16)
274 #define MVGBE_GEN_TCP_UDP_CHECKSUM		(1 << 17)
275 #define MVGBE_GEN_IP_V_4_CHECKSUM		(1 << 18)
276 #define MVGBE_ZERO_PADDING			(1 << 19)
277 #define MVGBE_TX_LAST_DESC			(1 << 20)
278 #define MVGBE_TX_FIRST_DESC			(1 << 21)
279 #define MVGBE_GEN_CRC				(1 << 22)
280 #define MVGBE_TX_EN_INTERRUPT			(1 << 23)
281 #define MVGBE_AUTO_MODE				(1 << 30)
282 
283 /* Address decode parameters */
284 /* Ethernet Base Address Register bits */
285 #define EBAR_TARGET_DRAM			0x00000000
286 #define EBAR_TARGET_DEVICE			0x00000001
287 #define EBAR_TARGET_CBS				0x00000002
288 #define EBAR_TARGET_PCI0			0x00000003
289 #define EBAR_TARGET_PCI1			0x00000004
290 #define EBAR_TARGET_CUNIT			0x00000005
291 #define EBAR_TARGET_AUNIT			0x00000006
292 #define EBAR_TARGET_GUNIT			0x00000007
293 
294 /* Window attrib */
295 #define EBAR_DRAM_CS0				0x00000E00
296 #define EBAR_DRAM_CS1				0x00000D00
297 #define EBAR_DRAM_CS2				0x00000B00
298 #define EBAR_DRAM_CS3				0x00000700
299 
300 /* DRAM Target interface */
301 #define EBAR_DRAM_NO_CACHE_COHERENCY		0x00000000
302 #define EBAR_DRAM_CACHE_COHERENCY_WT		0x00001000
303 #define EBAR_DRAM_CACHE_COHERENCY_WB		0x00002000
304 
305 /* Device Bus Target interface */
306 #define EBAR_DEVICE_DEVCS0			0x00001E00
307 #define EBAR_DEVICE_DEVCS1			0x00001D00
308 #define EBAR_DEVICE_DEVCS2			0x00001B00
309 #define EBAR_DEVICE_DEVCS3			0x00001700
310 #define EBAR_DEVICE_BOOTCS3			0x00000F00
311 
312 /* PCI Target interface */
313 #define EBAR_PCI_BYTE_SWAP			0x00000000
314 #define EBAR_PCI_NO_SWAP			0x00000100
315 #define EBAR_PCI_BYTE_WORD_SWAP			0x00000200
316 #define EBAR_PCI_WORD_SWAP			0x00000300
317 #define EBAR_PCI_NO_SNOOP_NOT_ASSERT		0x00000000
318 #define EBAR_PCI_NO_SNOOP_ASSERT		0x00000400
319 #define EBAR_PCI_IO_SPACE			0x00000000
320 #define EBAR_PCI_MEMORY_SPACE			0x00000800
321 #define EBAR_PCI_REQ64_FORCE			0x00000000
322 #define EBAR_PCI_REQ64_SIZE			0x00001000
323 
324 /* Window access control */
325 #define EWIN_ACCESS_NOT_ALLOWED 0
326 #define EWIN_ACCESS_READ_ONLY	1
327 #define EWIN_ACCESS_FULL	((1 << 1) | 1)
328 
329 /* structures represents Controller registers */
330 struct mvgbe_barsz {
331 	u32 bar;
332 	u32 size;
333 };
334 
335 struct mvgbe_rxcdp {
336 	struct mvgbe_rxdesc *rxcdp;
337 	u32 rxcdp_pad[3];
338 };
339 
340 struct mvgbe_tqx {
341 	u32 qxttbc;
342 	u32 tqxtbc;
343 	u32 tqxac;
344 	u32 tqxpad;
345 };
346 
347 struct mvgbe_registers {
348 	u32 phyadr;
349 	u32 smi;
350 	u32 euda;
351 	u32 eudid;
352 	u8 pad1[0x080 - 0x00c - 4];
353 	u32 euic;
354 	u32 euim;
355 	u8 pad2[0x094 - 0x084 - 4];
356 	u32 euea;
357 	u32 euiae;
358 	u8 pad3[0x0b0 - 0x098 - 4];
359 	u32 euc;
360 	u8 pad3a[0x200 - 0x0b0 - 4];
361 	struct mvgbe_barsz barsz[6];
362 	u8 pad4[0x280 - 0x22c - 4];
363 	u32 ha_remap[4];
364 	u32 bare;
365 	u32 epap;
366 	u8 pad5[0x400 - 0x294 - 4];
367 	u32 pxc;
368 	u32 pxcx;
369 	u32 mii_ser_params;
370 	u8 pad6[0x410 - 0x408 - 4];
371 	u32 evlane;
372 	u32 macal;
373 	u32 macah;
374 	u32 sdc;
375 	u32 dscp[7];
376 	u32 psc0;
377 	u32 vpt2p;
378 	u32 ps0;
379 	u32 tqc;
380 	u32 psc1;
381 	u32 ps1;
382 	u32 mrvl_header;
383 	u8 pad7[0x460 - 0x454 - 4];
384 	u32 ic;
385 	u32 ice;
386 	u32 pim;
387 	u32 peim;
388 	u8 pad8[0x474 - 0x46c - 4];
389 	u32 pxtfut;
390 	u32 pad9;
391 	u32 pxmfs;
392 	u32 pad10;
393 	u32 pxdfc;
394 	u32 pxofc;
395 	u8 pad11[0x494 - 0x488 - 4];
396 	u32 peuiae;
397 	u8 pad12[0x4bc - 0x494 - 4];
398 	u32 eth_type_prio;
399 	u8 pad13[0x4dc - 0x4bc - 4];
400 	u32 tqfpc;
401 	u32 pttbrc;
402 	u32 tqc1;
403 	u32 pmtu;
404 	u32 pmtbs;
405 	u8 pad14[0x60c - 0x4ec - 4];
406 	struct mvgbe_rxcdp rxcdp[7];
407 	struct mvgbe_rxdesc *rxcdp7;
408 	u32 rqc;
409 	struct mvgbe_txdesc *tcsdp;
410 	u8 pad15[0x6c0 - 0x684 - 4];
411 	struct mvgbe_txdesc *tcqdp[8];
412 	u8 pad16[0x700 - 0x6dc - 4];
413 	struct mvgbe_tqx tqx[8];
414 	u32 pttbc;
415 	u8 pad17[0x7a8 - 0x780 - 4];
416 	u32 tqxipg0;
417 	u32 pad18[3];
418 	u32 tqxipg1;
419 	u8 pad19[0x7c0 - 0x7b8 - 4];
420 	u32 hitkninlopkt;
421 	u32 hitkninasyncpkt;
422 	u32 lotkninasyncpkt;
423 	u32 pad20;
424 	u32 ts;
425 	u8 pad21[0x3000 - 0x27d0 - 4];
426 	u32 pad20_1[32];	/* mib counter registes */
427 	u8 pad22[0x3400 - 0x3000 - sizeof(u32) * 32];
428 	u32 dfsmt[64];
429 	u32 dfomt[64];
430 	u32 dfut[4];
431 	u8 pad23[0xe20c0 - 0x7360c - 4];
432 	u32 pmbus_top_arbiter;
433 };
434 
435 /* structures/enums needed by driver */
436 enum mvgbe_adrwin {
437 	MVGBE_WIN0,
438 	MVGBE_WIN1,
439 	MVGBE_WIN2,
440 	MVGBE_WIN3,
441 	MVGBE_WIN4,
442 	MVGBE_WIN5
443 };
444 
445 enum mvgbe_target {
446 	MVGBE_TARGET_DRAM,
447 	MVGBE_TARGET_DEV,
448 	MVGBE_TARGET_CBS,
449 	MVGBE_TARGET_PCI0,
450 	MVGBE_TARGET_PCI1
451 };
452 
453 struct mvgbe_winparam {
454 	enum mvgbe_adrwin win;	/* Window number */
455 	enum mvgbe_target target;	/* System targets */
456 	u16 attrib;		/* BAR attrib. See above macros */
457 	u32 base_addr;		/* Window base address in u32 form */
458 	u32 high_addr;		/* Window high address in u32 form */
459 	u32 size;		/* Size in MBytes. Must be % 64Kbyte. */
460 	int enable;		/* Enable/disable access to the window. */
461 	u16 access_ctrl;	/*Access ctrl register. see above macros */
462 };
463 
464 struct mvgbe_rxdesc {
465 	u32 cmd_sts;		/* Descriptor command status */
466 	u16 buf_size;		/* Buffer size */
467 	u16 byte_cnt;		/* Descriptor buffer byte count */
468 	u8 *buf_ptr;		/* Descriptor buffer pointer */
469 	struct mvgbe_rxdesc *nxtdesc_p;	/* Next descriptor pointer */
470 };
471 
472 struct mvgbe_txdesc {
473 	u32 cmd_sts;		/* Descriptor command status */
474 	u16 l4i_chk;		/* CPU provided TCP Checksum */
475 	u16 byte_cnt;		/* Descriptor buffer byte count */
476 	u8 *buf_ptr;		/* Descriptor buffer ptr */
477 	struct mvgbe_txdesc *nxtdesc_p;	/* Next descriptor ptr */
478 };
479 
480 /* port device data struct */
481 struct mvgbe_device {
482 	struct eth_device dev;
483 	struct mvgbe_registers *regs;
484 	struct mvgbe_txdesc *p_txdesc;
485 	struct mvgbe_rxdesc *p_rxdesc;
486 	struct mvgbe_rxdesc *p_rxdesc_curr;
487 	u8 *p_rxbuf;
488 	u8 *p_aligned_txbuf;
489 };
490 
491 #endif /* __MVGBE_H__ */
492