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Searched refs:MV_DRAM_INFO (Results 1 – 10 of 10) sorted by relevance

/external/u-boot/drivers/ddr/marvell/axp/
Dddr3_hw_training.h273 } MV_DRAM_INFO; typedef
329 int ddr3_sdram_pbs_compare(MV_DRAM_INFO *dram_info, u32 pup_locked, int is_tx,
334 int ddr3_sdram_dqs_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
339 int ddr3_sdram_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
344 int ddr3_sdram_direct_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
349 int ddr3_sdram_dm_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
353 int ddr3_load_patterns(MV_DRAM_INFO *dram_info, int resume);
355 int ddr3_read_leveling_hw(u32 freq, MV_DRAM_INFO *dram_info);
356 int ddr3_read_leveling_sw(u32 freq, int ratio_2to1, MV_DRAM_INFO *dram_info);
358 int ddr3_write_leveling_hw(u32 freq, MV_DRAM_INFO *dram_info);
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Dddr3_dqs.c67 int ddr3_find_adll_limits(MV_DRAM_INFO *dram_info, u32 cs, u32 ecc, int is_tx);
70 static int ddr3_center_calc(MV_DRAM_INFO *dram_info, u32 cs, u32 ecc,
72 int ddr3_special_pattern_i_search(MV_DRAM_INFO *dram_info, u32 cs, u32 ecc,
74 int ddr3_special_pattern_ii_search(MV_DRAM_INFO *dram_info, u32 cs, u32 ecc,
76 int ddr3_set_dqs_centralization_results(MV_DRAM_INFO *dram_info, u32 cs, u32 ecc,
92 static u32 *ddr3_dqs_choose_pattern(MV_DRAM_INFO *dram_info, u32 victim_dq) in ddr3_dqs_choose_pattern()
130 int ddr3_dqs_centralization_rx(MV_DRAM_INFO *dram_info) in ddr3_dqs_centralization_rx()
212 int ddr3_dqs_centralization_tx(MV_DRAM_INFO *dram_info) in ddr3_dqs_centralization_tx()
295 int ddr3_find_adll_limits(MV_DRAM_INFO *dram_info, u32 cs, u32 ecc, int is_tx) in ddr3_find_adll_limits()
886 static int ddr3_center_calc(MV_DRAM_INFO *dram_info, u32 cs, u32 ecc, in ddr3_center_calc()
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Dddr3_pbs.c59 static int ddr3_tx_shift_dqs_adll_step_before_fail(MV_DRAM_INFO *dram_info,
61 static int ddr3_rx_shift_dqs_to_first_fail(MV_DRAM_INFO *dram_info, u32 cur_pup,
63 static int ddr3_pbs_per_bit(MV_DRAM_INFO *dram_info, int *start_over, int is_tx,
65 static int ddr3_set_pbs_results(MV_DRAM_INFO *dram_info, int is_tx);
75 int ddr3_pbs_tx(MV_DRAM_INFO *dram_info) in ddr3_pbs_tx()
404 static int ddr3_tx_shift_dqs_adll_step_before_fail(MV_DRAM_INFO *dram_info, in ddr3_tx_shift_dqs_adll_step_before_fail()
519 int ddr3_pbs_rx(MV_DRAM_INFO *dram_info) in ddr3_pbs_rx()
916 static int ddr3_rx_shift_dqs_to_first_fail(MV_DRAM_INFO *dram_info, u32 cur_pup, in ddr3_rx_shift_dqs_to_first_fail()
1136 static int ddr3_pbs_per_bit(MV_DRAM_INFO *dram_info, int *start_over, int is_tx, in ddr3_pbs_per_bit()
1416 static int ddr3_set_pbs_results(MV_DRAM_INFO *dram_info, int is_tx) in ddr3_set_pbs_results()
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Dddr3_hw_training.c84 MV_DRAM_INFO dram_info; in ddr3_hw_training()
484 void ddr3_set_performance_params(MV_DRAM_INFO *dram_info) in ddr3_set_performance_params()
619 int ddr3_load_patterns(MV_DRAM_INFO *dram_info, int resume) in ddr3_load_patterns()
695 void ddr3_save_training(MV_DRAM_INFO *dram_info) in ddr3_save_training()
869 int ddr3_check_if_resume_mode(MV_DRAM_INFO *dram_info, u32 freq) in ddr3_check_if_resume_mode()
913 int ddr3_training_suspend_resume(MV_DRAM_INFO *dram_info) in ddr3_training_suspend_resume()
1045 int ddr3_get_min_max_rl_phase(MV_DRAM_INFO *dram_info, u32 *min, u32 *max, in ddr3_get_min_max_rl_phase()
1085 int ddr3_odt_read_dynamic_config(MV_DRAM_INFO *dram_info) in ddr3_odt_read_dynamic_config()
Dddr3_sdram.c163 int ddr3_sdram_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup, in ddr3_sdram_compare()
219 int ddr3_sdram_dm_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup, in ddr3_sdram_dm_compare()
280 int ddr3_sdram_pbs_compare(MV_DRAM_INFO *dram_info, u32 pup_locked, in ddr3_sdram_pbs_compare()
441 int ddr3_sdram_direct_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup, in ddr3_sdram_direct_compare()
599 int ddr3_sdram_dqs_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup, in ddr3_sdram_dqs_compare()
Dddr3_write_leveling.c48 MV_DRAM_INFO *dram_info);
64 int ddr3_write_leveling_hw(u32 freq, MV_DRAM_INFO *dram_info) in ddr3_write_leveling_hw()
184 int ddr3_wl_supplement(MV_DRAM_INFO *dram_info) in ddr3_wl_supplement()
472 int ddr3_write_leveling_hw_reg_dimm(u32 freq, MV_DRAM_INFO *dram_info) in ddr3_write_leveling_hw_reg_dimm()
657 int ddr3_write_leveling_sw(u32 freq, int ratio_2to1, MV_DRAM_INFO *dram_info) in ddr3_write_leveling_sw()
882 MV_DRAM_INFO *dram_info) in ddr3_write_leveling_sw_reg_dimm()
1125 u32 *result, MV_DRAM_INFO *dram_info) in ddr3_write_leveling_single_cs()
Dddr3_read_leveling.c46 MV_DRAM_INFO *dram_info);
50 MV_DRAM_INFO *dram_info);
61 int ddr3_read_leveling_hw(u32 freq, MV_DRAM_INFO *dram_info) in ddr3_read_leveling_hw()
179 int ddr3_read_leveling_sw(u32 freq, int ratio_2to1, MV_DRAM_INFO *dram_info) in ddr3_read_leveling_sw()
335 static void overrun(u32 cs, MV_DRAM_INFO *info, u32 pup, u32 locked_pups, in overrun()
401 MV_DRAM_INFO *dram_info) in ddr3_read_leveling_single_cs_rl_mode()
753 MV_DRAM_INFO *dram_info) in ddr3_read_leveling_single_cs_window_mode()
Dxor.h64 void mv_sys_xor_init(MV_DRAM_INFO *dram_info);
Dxor.c23 void mv_sys_xor_init(MV_DRAM_INFO *dram_info) in mv_sys_xor_init()
Dddr3_dfs.c112 int ddr3_dfs_high_2_low(u32 freq, MV_DRAM_INFO *dram_info) in ddr3_dfs_high_2_low()
768 int ddr3_dfs_low_2_high(u32 freq, int ratio_2to1, MV_DRAM_INFO *dram_info) in ddr3_dfs_low_2_high()