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Searched refs:MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_RD (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/arch/arm/include/asm/arch-mx5/
Dcrm_regs.h184 #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_RD(r) (((r) >> 16) & 0x3) macro
/external/u-boot/arch/arm/mach-imx/mx5/
Dclock.c396 clk_sel = MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_RD(cscmr1); in get_esdhc_clk()