Searched refs:MXS_DMA_DESC_WAIT4END (Results 1 – 3 of 3) sorted by relevance
312 MXS_DMA_DESC_WAIT4END | (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET) | in mxs_nand_cmd_ctrl()428 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END | in mxs_nand_read_buf()455 MXS_DMA_DESC_WAIT4END | (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET); in mxs_nand_read_buf()514 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END | in mxs_nand_write_buf()569 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END | in mxs_nand_ecc_read_page()586 MXS_DMA_DESC_WAIT4END | (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET); in mxs_nand_ecc_read_page()611 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END | in mxs_nand_ecc_read_page()724 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END | in mxs_nand_ecc_write_page()
89 #define MXS_DMA_DESC_WAIT4END (1 << 7) macro
233 MXS_DMA_DESC_WAIT4END | in video_hw_init()