Searched refs:MidRegLo (Results 1 – 2 of 2) sorted by relevance
2876 unsigned MidRegLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in splitScalar64BitBFE() local2880 BuildMI(MBB, MII, DL, get(AMDGPU::V_BFE_I32), MidRegLo) in splitScalar64BitBFE()2887 .addReg(MidRegLo); in splitScalar64BitBFE()2890 .addReg(MidRegLo) in splitScalar64BitBFE()
4418 unsigned MidRegLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in splitScalar64BitBFE() local4422 BuildMI(MBB, MII, DL, get(AMDGPU::V_BFE_I32), MidRegLo) in splitScalar64BitBFE()4429 .addReg(MidRegLo); in splitScalar64BitBFE()4432 .addReg(MidRegLo) in splitScalar64BitBFE()