| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.td | 119 class T_ALU32_3op<string mnemonic, bits<3> MajOp, bits<3> MinOp, bit OpsRev,
135 let Inst{23-21} = MinOp;
142 class T_ALU32_3op_pred<string mnemonic, bits<3> MajOp, bits<3> MinOp,
162 let Inst{23-21} = MinOp;
171 class T_ALU32_combineh<string Op1, string Op2, bits<3> MajOp, bits<3> MinOp,
173 : T_ALU32_3op<"", MajOp, MinOp, OpsRev, 0> {
183 bits<3> MinOp, bit OpsRev, bit IsComm>
184 : T_ALU32_3op<"", MajOp, MinOp, OpsRev, IsComm> {
206 multiclass T_ALU32_3op_p<string mnemonic, bits<3> MajOp, bits<3> MinOp,
208 def t : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 0, 0>;
[all …]
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| D | HexagonInstrInfoV5.td | 151 class T_MInstFloat <string mnemonic, bits<3> MajOp, bits<3> MinOp>
168 let Inst{7-5} = MinOp;
239 class T_fcmp <string mnemonic, RegisterClass RC, bits<3> MinOp,
254 let Inst{7-5} = MinOp;
258 class T_fcmp64 <string mnemonic, PatFrag OpNode, bits<3> MinOp>
259 : T_fcmp <mnemonic, DoubleRegs, MinOp,
265 class T_fcmp32 <string mnemonic, PatFrag OpNode, bits<3> MinOp>
266 : T_fcmp <mnemonic, IntRegs, MinOp,
529 class F2_RDD_RSS_CONVERT<string mnemonic, bits<3> MinOp,
543 let Inst{7-5} = MinOp;
[all …]
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| D | HexagonInstrInfoV3.td | 100 class T_ALU64_addsp_hl<string suffix, bits<3> MinOp>
101 : T_ALU64_rr<"add", suffix, 0b0011, 0b011, MinOp, 0, 0, "">;
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| D | HexagonInstrInfoVector.td | 53 class vshift_v4i16<SDNode Op, string Str, bits<3>MajOp, bits<3>MinOp>
54 : S_2OpInstImm<Str, MajOp, MinOp, u4Imm,
61 class vshift_v2i32<SDNode Op, string Str, bits<3>MajOp, bits<3>MinOp>
62 : S_2OpInstImm<Str, MajOp, MinOp, u5Imm,
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| D | HexagonInstrInfoV4.td | 128 class T_ALU32_3op_not<string mnemonic, bits<3> MajOp, bits<3> MinOp,
130 : T_ALU32_3op<mnemonic, MajOp, MinOp, OpsRev, 0> {
164 class T_CMP_rrbh<string mnemonic, bits<3> MinOp, bit IsComm>
182 let Inst{7-5} = MinOp;
2721 class T_S3op_6 <string mnemonic, bits<3> MinOp, bit isUnsigned>
2736 let Inst{7-5} = MinOp;
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| /external/tensorflow/tensorflow/compiler/tf2xla/kernels/ |
| D | reduction_ops.cc | 66 class MinOp : public XlaReductionOp { class
68 explicit MinOp(OpKernelConstruction* ctx) in MinOp() function in tensorflow::__anon48fb755d0111::MinOp
82 MinOp);
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| /external/tensorflow/tensorflow/c/eager/ |
| D | c_api_test_util.h | 53 TFE_Op* MinOp(TFE_Context* ctx, TFE_TensorHandle* input,
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| D | c_api_test_util.cc | 158 TFE_Op* MinOp(TFE_Context* ctx, TFE_TensorHandle* input, in MinOp() function
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| D | c_api_test.cc | 1016 TFE_Op* minOp = MinOp(ctx, input, axis); in TEST()
1093 TFE_Op* minOp = MinOp(ctx, input, axis); in Execute_Min_XLA_CPU()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonPseudo.td | 43 class REG_IMMED<string RegHalf, bit Rs, bits<3> MajOp, bit MinOp,
54 let Inst{21} = MinOp;
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| /external/tensorflow/tensorflow/core/kernels/ |
| D | segment_reduction_ops.cc | 421 struct MinOp { struct
525 functor::MinOp<type>); \
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| /external/tensorflow/tensorflow/c/ |
| D | c_api_experimental_test.cc | 400 TFE_Op* op = MinOp(eager_ctx_, axis, axis); in TEST_F()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 2953 unsigned MinOp = std::min(Op1, Op2); in swapMIOperands() local
2954 MachineOperand MOp1 = MI.getOperand(MinOp); in swapMIOperands()
2961 if (MaxOp - MinOp == 1 && MI.getNumOperands() == MinOp) { in swapMIOperands()
2969 for (unsigned i = MI.getNumOperands() - 1; i >= MinOp; i--) { in swapMIOperands()
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