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Searched refs:Mips (Results 1 – 25 of 345) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/Target/Mips/MCTargetDesc/
DMipsBaseInfo.h27 case Mips::ZERO: case Mips::ZERO_64: case Mips::F0: case Mips::D0_64: in getMipsRegisterNumbering()
28 case Mips::D0: in getMipsRegisterNumbering()
30 case Mips::AT: case Mips::AT_64: case Mips::F1: case Mips::D1_64: in getMipsRegisterNumbering()
32 case Mips::V0: case Mips::V0_64: case Mips::F2: case Mips::D2_64: in getMipsRegisterNumbering()
33 case Mips::D1: in getMipsRegisterNumbering()
35 case Mips::V1: case Mips::V1_64: case Mips::F3: case Mips::D3_64: in getMipsRegisterNumbering()
37 case Mips::A0: case Mips::A0_64: case Mips::F4: case Mips::D4_64: in getMipsRegisterNumbering()
38 case Mips::D2: in getMipsRegisterNumbering()
40 case Mips::A1: case Mips::A1_64: case Mips::F5: case Mips::D5_64: in getMipsRegisterNumbering()
42 case Mips::A2: case Mips::A2_64: case Mips::F6: case Mips::D6_64: in getMipsRegisterNumbering()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMipsRegisterInfo.cpp46 : MipsGenRegisterInfo(Mips::RA), Subtarget(ST), TII(tii) {} in MipsRegisterInfo()
54 case Mips::ZERO: case Mips::ZERO_64: case Mips::F0: case Mips::D0_64: in getRegisterNumbering()
55 case Mips::D0: in getRegisterNumbering()
57 case Mips::AT: case Mips::AT_64: case Mips::F1: case Mips::D1_64: in getRegisterNumbering()
59 case Mips::V0: case Mips::V0_64: case Mips::F2: case Mips::D2_64: in getRegisterNumbering()
60 case Mips::D1: in getRegisterNumbering()
62 case Mips::V1: case Mips::V1_64: case Mips::F3: case Mips::D3_64: in getRegisterNumbering()
64 case Mips::A0: case Mips::A0_64: case Mips::F4: case Mips::D4_64: in getRegisterNumbering()
65 case Mips::D2: in getRegisterNumbering()
67 case Mips::A1: case Mips::A1_64: case Mips::F5: case Mips::D5_64: in getRegisterNumbering()
[all …]
DMipsInstrInfo.cpp30 : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP), in MipsInstrInfo()
53 if ((Opc == Mips::LW) || (Opc == Mips::LW_P8) || (Opc == Mips::LD) || in isLoadFromStackSlot()
54 (Opc == Mips::LD_P8) || (Opc == Mips::LWC1) || (Opc == Mips::LWC1_P8) || in isLoadFromStackSlot()
55 (Opc == Mips::LDC1) || (Opc == Mips::LDC164) || in isLoadFromStackSlot()
56 (Opc == Mips::LDC164_P8)) { in isLoadFromStackSlot()
78 if ((Opc == Mips::SW) || (Opc == Mips::SW_P8) || (Opc == Mips::SD) || in isStoreToStackSlot()
79 (Opc == Mips::SD_P8) || (Opc == Mips::SWC1) || (Opc == Mips::SWC1_P8) || in isStoreToStackSlot()
80 (Opc == Mips::SDC1) || (Opc == Mips::SDC164) || in isStoreToStackSlot()
81 (Opc == Mips::SDC164_P8)) { in isStoreToStackSlot()
98 BuildMI(MBB, MI, DL, get(Mips::NOP)); in insertNoop()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsSEInstrInfo.cpp30 return STI.isPositionIndependent() ? Mips::B_MM : Mips::J_MM; in getUnconditionalBranch()
31 return STI.isPositionIndependent() ? Mips::B : Mips::J; in getUnconditionalBranch()
50 if ((Opc == Mips::LW) || (Opc == Mips::LD) || in isLoadFromStackSlot()
51 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) { in isLoadFromStackSlot()
72 if ((Opc == Mips::SW) || (Opc == Mips::SD) || in isStoreToStackSlot()
73 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) { in isStoreToStackSlot()
91 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg. in copyPhysReg()
92 if (Mips::GPR32RegClass.contains(SrcReg)) { in copyPhysReg()
94 Opc = Mips::MOVE16_MM; in copyPhysReg()
96 Opc = Mips::OR, ZeroReg = Mips::ZERO; in copyPhysReg()
[all …]
DMipsInstrInfo.cpp41 : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP), in MipsInstrInfo()
62 BuildMI(MBB, MI, DL, get(Mips::NOP)); in insertNoop()
281 case Mips::B: in isBranchOffsetInRange()
282 case Mips::BAL: in isBranchOffsetInRange()
283 case Mips::BC1F: in isBranchOffsetInRange()
284 case Mips::BC1FL: in isBranchOffsetInRange()
285 case Mips::BC1T: in isBranchOffsetInRange()
286 case Mips::BC1TL: in isBranchOffsetInRange()
287 case Mips::BEQ: case Mips::BEQ64: in isBranchOffsetInRange()
288 case Mips::BEQL: in isBranchOffsetInRange()
[all …]
DMipsExpandPseudo.cpp85 unsigned ZERO = Mips::ZERO; in expandAtomicCmpSwapSubword()
86 unsigned BNE = Mips::BNE; in expandAtomicCmpSwapSubword()
87 unsigned BEQ = Mips::BEQ; in expandAtomicCmpSwapSubword()
89 I->getOpcode() == Mips::ATOMIC_CMP_SWAP_I8_POSTRA ? Mips::SEB : Mips::SEH; in expandAtomicCmpSwapSubword()
92 LL = STI->hasMips32r6() ? Mips::LL_MMR6 : Mips::LL_MM; in expandAtomicCmpSwapSubword()
93 SC = STI->hasMips32r6() ? Mips::SC_MMR6 : Mips::SC_MM; in expandAtomicCmpSwapSubword()
94 BNE = STI->hasMips32r6() ? Mips::BNEC_MMR6 : Mips::BNE_MM; in expandAtomicCmpSwapSubword()
95 BEQ = STI->hasMips32r6() ? Mips::BEQC_MMR6 : Mips::BEQ_MM; in expandAtomicCmpSwapSubword()
97 LL = STI->hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) in expandAtomicCmpSwapSubword()
98 : (ArePtrs64bit ? Mips::LL64 : Mips::LL); in expandAtomicCmpSwapSubword()
[all …]
DMips16InstrInfo.cpp44 : MipsInstrInfo(STI, Mips::Bimm16) {} in Mips16InstrInfo()
76 if (Mips::CPU16RegsRegClass.contains(DestReg) && in copyPhysReg()
77 Mips::GPR32RegClass.contains(SrcReg)) in copyPhysReg()
78 Opc = Mips::MoveR3216; in copyPhysReg()
79 else if (Mips::GPR32RegClass.contains(DestReg) && in copyPhysReg()
80 Mips::CPU16RegsRegClass.contains(SrcReg)) in copyPhysReg()
81 Opc = Mips::Move32R16; in copyPhysReg()
82 else if ((SrcReg == Mips::HI0) && in copyPhysReg()
83 (Mips::CPU16RegsRegClass.contains(DestReg))) in copyPhysReg()
84 Opc = Mips::Mfhi16, SrcReg = 0; in copyPhysReg()
[all …]
DMipsRegisterInfo.cpp43 MipsRegisterInfo::MipsRegisterInfo() : MipsGenRegisterInfo(Mips::RA) {} in MipsRegisterInfo()
45 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; } in getPICCallReg()
55 return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in getPointerRegClass()
57 return &Mips::GPRMM16RegClass; in getPointerRegClass()
59 return ABI.ArePtrs64bit() ? &Mips::SP64RegClass : &Mips::SP32RegClass; in getPointerRegClass()
61 return ABI.ArePtrs64bit() ? &Mips::GP64RegClass : &Mips::GP32RegClass; in getPointerRegClass()
73 case Mips::GPR32RegClassID: in getRegPressureLimit()
74 case Mips::GPR64RegClassID: in getRegPressureLimit()
75 case Mips::DSPRRegClassID: { in getRegPressureLimit()
79 case Mips::FGR32RegClassID: in getRegPressureLimit()
[all …]
DMicroMipsSizeReduction.cpp210 {RT_OneInstr, OpCodes(Mips::ADDiu, Mips::ADDIUR1SP_MM),
212 {RT_OneInstr, OpCodes(Mips::ADDiu, Mips::ADDIUSP_MM), ReduceADDIUToADDIUSP,
214 {RT_OneInstr, OpCodes(Mips::ADDiu_MM, Mips::ADDIUR1SP_MM),
216 {RT_OneInstr, OpCodes(Mips::ADDiu_MM, Mips::ADDIUSP_MM),
218 {RT_OneInstr, OpCodes(Mips::ADDu, Mips::ADDU16_MM),
221 {RT_OneInstr, OpCodes(Mips::ADDu_MM, Mips::ADDU16_MM),
224 {RT_OneInstr, OpCodes(Mips::LBu, Mips::LBU16_MM), ReduceLXUtoLXU16,
226 {RT_OneInstr, OpCodes(Mips::LBu_MM, Mips::LBU16_MM), ReduceLXUtoLXU16,
228 {RT_OneInstr, OpCodes(Mips::LEA_ADDiu, Mips::ADDIUR1SP_MM),
230 {RT_OneInstr, OpCodes(Mips::LEA_ADDiu_MM, Mips::ADDIUR1SP_MM),
[all …]
DMipsSERegisterInfo.cpp57 return &Mips::GPR32RegClass; in intRegClass()
60 return &Mips::GPR64RegClass; in intRegClass()
69 case Mips::LD_B: in getLoadStoreOffsetSizeInBits()
70 case Mips::ST_B: in getLoadStoreOffsetSizeInBits()
72 case Mips::LD_H: in getLoadStoreOffsetSizeInBits()
73 case Mips::ST_H: in getLoadStoreOffsetSizeInBits()
75 case Mips::LD_W: in getLoadStoreOffsetSizeInBits()
76 case Mips::ST_W: in getLoadStoreOffsetSizeInBits()
78 case Mips::LD_D: in getLoadStoreOffsetSizeInBits()
79 case Mips::ST_D: in getLoadStoreOffsetSizeInBits()
[all …]
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenRegisterInfo.inc18 namespace Mips {
440 } // end namespace Mips
444 namespace Mips {
521 } // end namespace Mips
526 namespace Mips {
542 } // end namespace Mips
1522 { Mips::AT },
1523 { Mips::DSPCCond },
1524 { Mips::DSPCarry },
1525 { Mips::DSPEFI },
[all …]
DMipsGenCallingConv.inc97 Mips::V0, Mips::V1, Mips::A0, Mips::A1
153 …Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T…
156 …Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, Mips::D16_64, Mips::D17_64, Mips::D18_64, …
166 Mips::F12, Mips::F13, Mips::F14, Mips::F15, Mips::F16, Mips::F17, Mips::F18, Mips::F19
169 …Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T…
179 …Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, Mips::D16_64, Mips::D17_64, Mips::D18_64, …
182 …Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T…
213 …Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T…
223 …Mips::D0_64, Mips::D1_64, Mips::D2_64, Mips::D3_64, Mips::D4_64, Mips::D5_64, Mips::D6_64, Mips::D…
247 Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3
[all …]
DMipsGenMCCodeEmitter.inc2648 case Mips::Break16:
2649 case Mips::DERET:
2650 case Mips::DERET_MM:
2651 case Mips::DERET_MMR6:
2652 case Mips::EHB:
2653 case Mips::EHB_MM:
2654 case Mips::EHB_MMR6:
2655 case Mips::ERET:
2656 case Mips::ERETNC:
2657 case Mips::ERETNC_MMR6:
[all …]
DMipsGenMCPseudoLowering.inc14 case Mips::AND_V_D_PSEUDO: {
17 TmpInst.setOpcode(Mips::AND_V);
30 case Mips::AND_V_H_PSEUDO: {
33 TmpInst.setOpcode(Mips::AND_V);
46 case Mips::AND_V_W_PSEUDO: {
49 TmpInst.setOpcode(Mips::AND_V);
62 case Mips::B: {
65 TmpInst.setOpcode(Mips::BEQ);
67 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
69 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
[all …]
/external/llvm/lib/Target/Mips/
DMipsSEInstrInfo.cpp29 : MipsInstrInfo(STI, STI.isPositionIndependent() ? Mips::B : Mips::J), in MipsSEInstrInfo()
45 if ((Opc == Mips::LW) || (Opc == Mips::LD) || in isLoadFromStackSlot()
46 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) { in isLoadFromStackSlot()
67 if ((Opc == Mips::SW) || (Opc == Mips::SD) || in isStoreToStackSlot()
68 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) { in isStoreToStackSlot()
86 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg. in copyPhysReg()
87 if (Mips::GPR32RegClass.contains(SrcReg)) { in copyPhysReg()
89 Opc = Mips::MOVE16_MM; in copyPhysReg()
91 Opc = Mips::OR, ZeroReg = Mips::ZERO; in copyPhysReg()
92 } else if (Mips::CCRRegClass.contains(SrcReg)) in copyPhysReg()
[all …]
DMips16InstrInfo.cpp33 : MipsInstrInfo(STI, Mips::Bimm16), RI() {} in Mips16InstrInfo()
65 if (Mips::CPU16RegsRegClass.contains(DestReg) && in copyPhysReg()
66 Mips::GPR32RegClass.contains(SrcReg)) in copyPhysReg()
67 Opc = Mips::MoveR3216; in copyPhysReg()
68 else if (Mips::GPR32RegClass.contains(DestReg) && in copyPhysReg()
69 Mips::CPU16RegsRegClass.contains(SrcReg)) in copyPhysReg()
70 Opc = Mips::Move32R16; in copyPhysReg()
71 else if ((SrcReg == Mips::HI0) && in copyPhysReg()
72 (Mips::CPU16RegsRegClass.contains(DestReg))) in copyPhysReg()
73 Opc = Mips::Mfhi16, SrcReg = 0; in copyPhysReg()
[all …]
DMipsRegisterInfo.cpp45 MipsRegisterInfo::MipsRegisterInfo() : MipsGenRegisterInfo(Mips::RA) {} in MipsRegisterInfo()
47 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; } in getPICCallReg()
57 return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in getPointerRegClass()
59 return ABI.ArePtrs64bit() ? &Mips::GPRMM16_64RegClass in getPointerRegClass()
60 : &Mips::GPRMM16RegClass; in getPointerRegClass()
62 return ABI.ArePtrs64bit() ? &Mips::SP64RegClass : &Mips::SP32RegClass; in getPointerRegClass()
64 return ABI.ArePtrs64bit() ? &Mips::GP64RegClass : &Mips::GP32RegClass; in getPointerRegClass()
76 case Mips::GPR32RegClassID: in getRegPressureLimit()
77 case Mips::GPR64RegClassID: in getRegPressureLimit()
78 case Mips::DSPRRegClassID: { in getRegPressureLimit()
[all …]
DMipsInstrInfo.cpp33 : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP), in MipsInstrInfo()
54 BuildMI(MBB, MI, DL, get(Mips::NOP)); in insertNoop()
270 case Mips::BNE: in getEquivalentCompactForm()
271 case Mips::BEQ: in getEquivalentCompactForm()
279 case Mips::JR: in getEquivalentCompactForm()
280 case Mips::PseudoReturn: in getEquivalentCompactForm()
281 case Mips::PseudoIndirectBranch: in getEquivalentCompactForm()
290 (I->getOperand(0).getReg() == Mips::ZERO || in getEquivalentCompactForm()
291 I->getOperand(0).getReg() == Mips::ZERO_64)) && in getEquivalentCompactForm()
293 (I->getOperand(1).getReg() == Mips::ZERO || in getEquivalentCompactForm()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/MCTargetDesc/
DMipsAsmBackend.cpp49 case Mips::fixup_Mips_LO16: in adjustFixupValue()
50 case Mips::fixup_Mips_GPREL16: in adjustFixupValue()
51 case Mips::fixup_Mips_GPOFF_HI: in adjustFixupValue()
52 case Mips::fixup_Mips_GPOFF_LO: in adjustFixupValue()
53 case Mips::fixup_Mips_GOT_PAGE: in adjustFixupValue()
54 case Mips::fixup_Mips_GOT_OFST: in adjustFixupValue()
55 case Mips::fixup_Mips_GOT_DISP: in adjustFixupValue()
56 case Mips::fixup_Mips_GOT_LO16: in adjustFixupValue()
57 case Mips::fixup_Mips_CALL_LO16: in adjustFixupValue()
58 case Mips::fixup_MICROMIPS_GPOFF_HI: in adjustFixupValue()
[all …]
DMipsABIInfo.cpp19 static const MCPhysReg O32IntRegs[4] = {Mips::A0, Mips::A1, Mips::A2, Mips::A3};
22 Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
23 Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64};
66 return ArePtrs64bit() ? Mips::SP_64 : Mips::SP; in GetStackPtr()
70 return ArePtrs64bit() ? Mips::FP_64 : Mips::FP; in GetFramePtr()
74 return ArePtrs64bit() ? Mips::S7_64 : Mips::S7; in GetBasePtr()
78 return ArePtrs64bit() ? Mips::GP_64 : Mips::GP; in GetGlobalPtr()
82 return ArePtrs64bit() ? Mips::ZERO_64 : Mips::ZERO; in GetNullPtr()
86 return AreGprs64bit() ? Mips::ZERO_64 : Mips::ZERO; in GetZeroReg()
90 return ArePtrs64bit() ? Mips::DADDu : Mips::ADDu; in GetPtrAdduOp()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp117 Mips::FeatureMips1, Mips::FeatureMips2, Mips::FeatureMips3,
118 Mips::FeatureMips3_32, Mips::FeatureMips3_32r2, Mips::FeatureMips4,
119 Mips::FeatureMips4_32, Mips::FeatureMips4_32r2, Mips::FeatureMips5,
120 Mips::FeatureMips5_32r2, Mips::FeatureMips32, Mips::FeatureMips32r2,
121 Mips::FeatureMips32r3, Mips::FeatureMips32r5, Mips::FeatureMips32r6,
122 Mips::FeatureMips64, Mips::FeatureMips64r2, Mips::FeatureMips64r3,
123 Mips::FeatureMips64r5, Mips::FeatureMips64r6, Mips::FeatureCnMips,
124 Mips::FeatureFP64Bit, Mips::FeatureGP64Bit, Mips::FeatureNaN2008
530 return getSTI().getFeatureBits()[Mips::FeatureGP64Bit]; in isGP64bit()
534 return getSTI().getFeatureBits()[Mips::FeatureFP64Bit]; in isFP64bit()
[all …]
/external/llvm/lib/Target/Mips/MCTargetDesc/
DMipsABIInfo.cpp19 static const MCPhysReg O32IntRegs[4] = {Mips::A0, Mips::A1, Mips::A2, Mips::A3};
22 Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
23 Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64};
67 return ArePtrs64bit() ? Mips::SP_64 : Mips::SP; in GetStackPtr()
71 return ArePtrs64bit() ? Mips::FP_64 : Mips::FP; in GetFramePtr()
75 return ArePtrs64bit() ? Mips::S7_64 : Mips::S7; in GetBasePtr()
79 return ArePtrs64bit() ? Mips::GP_64 : Mips::GP; in GetGlobalPtr()
83 return ArePtrs64bit() ? Mips::ZERO_64 : Mips::ZERO; in GetNullPtr()
87 return AreGprs64bit() ? Mips::ZERO_64 : Mips::ZERO; in GetZeroReg()
91 return ArePtrs64bit() ? Mips::DADDu : Mips::ADDu; in GetPtrAdduOp()
[all …]
DMipsMCCodeEmitter.cpp69 case Mips::DSLL: in LowerLargeShift()
70 Inst.setOpcode(Mips::DSLL32); in LowerLargeShift()
72 case Mips::DSRL: in LowerLargeShift()
73 Inst.setOpcode(Mips::DSRL32); in LowerLargeShift()
75 case Mips::DSRA: in LowerLargeShift()
76 Inst.setOpcode(Mips::DSRA32); in LowerLargeShift()
78 case Mips::DROTR: in LowerLargeShift()
79 Inst.setOpcode(Mips::DROTR32); in LowerLargeShift()
81 case Mips::DSLL_MM64R6: in LowerLargeShift()
82 Inst.setOpcode(Mips::DSLL32_MM64R6); in LowerLargeShift()
[all …]
/external/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp94 Mips::FeatureMips1, Mips::FeatureMips2, Mips::FeatureMips3,
95 Mips::FeatureMips3_32, Mips::FeatureMips3_32r2, Mips::FeatureMips4,
96 Mips::FeatureMips4_32, Mips::FeatureMips4_32r2, Mips::FeatureMips5,
97 Mips::FeatureMips5_32r2, Mips::FeatureMips32, Mips::FeatureMips32r2,
98 Mips::FeatureMips32r3, Mips::FeatureMips32r5, Mips::FeatureMips32r6,
99 Mips::FeatureMips64, Mips::FeatureMips64r2, Mips::FeatureMips64r3,
100 Mips::FeatureMips64r5, Mips::FeatureMips64r6, Mips::FeatureCnMips,
101 Mips::FeatureFP64Bit, Mips::FeatureGP64Bit, Mips::FeatureNaN2008
447 return getSTI().getFeatureBits()[Mips::FeatureGP64Bit]; in isGP64bit()
450 return getSTI().getFeatureBits()[Mips::FeatureFP64Bit]; in isFP64bit()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/InstPrinter/
DMipsInstPrinter.cpp37 const char* Mips::MipsFCCToString(Mips::CondCode CC) { in MipsFCCToString()
84 case Mips::RDHWR: in printInst()
85 case Mips::RDHWR64: in printInst()
89 case Mips::Save16: in printInst()
94 case Mips::SaveX16: in printInst()
99 case Mips::Restore16: in printInst()
104 case Mips::RestoreX16: in printInst()
119 case Mips::RDHWR: in printInst()
120 case Mips::RDHWR64: in printInst()
168 case Mips::SWM32_MM: in printMemOperand()
[all …]

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