| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | MLxExpansionPass.cpp | 66 unsigned MulOpc, unsigned AddSubOpc,
207 unsigned MulOpc, unsigned AddSubOpc, in ExpandFPMLxInstruction() argument
221 const MCInstrDesc &MCID1 = TII->get(MulOpc); in ExpandFPMLxInstruction()
292 unsigned MulOpc, AddSubOpc; in ExpandFPMLxInstructions() local
295 MulOpc, AddSubOpc, NegAcc, HasLane) || in ExpandFPMLxInstructions()
299 ExpandFPMLxInstruction(MBB, MI, MulOpc, AddSubOpc, NegAcc, HasLane); in ExpandFPMLxInstructions()
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| D | ARMBaseInstrInfo.h | 281 bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
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| D | ARMBaseInstrInfo.cpp | 56 unsigned MulOpc; // Expanded multiplication opcode member
92 MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc); in ARMBaseInstrInfo()
2754 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc, in isFpMLxInstruction() argument
2762 MulOpc = Entry.MulOpc; in isFpMLxInstruction()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | MLxExpansionPass.cpp | 69 unsigned MulOpc, unsigned AddSubOpc,
273 unsigned MulOpc, unsigned AddSubOpc, in ExpandFPMLxInstruction() argument
287 const MCInstrDesc &MCID1 = TII->get(MulOpc); in ExpandFPMLxInstruction()
357 unsigned MulOpc, AddSubOpc; in ExpandFPMLxInstructions() local
360 MulOpc, AddSubOpc, NegAcc, HasLane) || in ExpandFPMLxInstructions()
364 ExpandFPMLxInstruction(MBB, MI, MulOpc, AddSubOpc, NegAcc, HasLane); in ExpandFPMLxInstructions()
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| D | ARMBaseInstrInfo.h | 413 bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
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| D | ARMBaseInstrInfo.cpp | 81 uint16_t MulOpc; // Expanded multiplication opcode member
117 MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc); in ARMBaseInstrInfo()
4543 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc, in isFpMLxInstruction() argument
4551 MulOpc = Entry.MulOpc; in isFpMLxInstruction()
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| /external/llvm/lib/Target/ARM/ |
| D | MLxExpansionPass.cpp | 69 unsigned MulOpc, unsigned AddSubOpc,
273 unsigned MulOpc, unsigned AddSubOpc, in ExpandFPMLxInstruction() argument
287 const MCInstrDesc &MCID1 = TII->get(MulOpc); in ExpandFPMLxInstruction()
360 unsigned MulOpc, AddSubOpc; in ExpandFPMLxInstructions() local
363 MulOpc, AddSubOpc, NegAcc, HasLane) || in ExpandFPMLxInstructions()
367 ExpandFPMLxInstruction(MBB, MI, MulOpc, AddSubOpc, NegAcc, HasLane); in ExpandFPMLxInstructions()
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| D | ARMBaseInstrInfo.h | 382 bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
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| D | ARMBaseInstrInfo.cpp | 57 uint16_t MulOpc; // Expanded multiplication opcode member
93 MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc); in ARMBaseInstrInfo()
4149 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc, in isFpMLxInstruction() argument
4157 MulOpc = Entry.MulOpc; in isFpMLxInstruction()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 2880 unsigned MulOpc, unsigned ZeroReg) { in canCombineWithMUL() argument
2881 return canCombine(MBB, MO, MulOpc, ZeroReg, true); in canCombineWithMUL()
2887 unsigned MulOpc) { in canCombineWithFMUL() argument
2888 return canCombine(MBB, MO, MulOpc); in canCombineWithFMUL()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 3589 unsigned MulOpc, unsigned ZeroReg) { in canCombineWithMUL() argument
3590 return canCombine(MBB, MO, MulOpc, ZeroReg, true); in canCombineWithMUL()
3596 unsigned MulOpc) { in canCombineWithFMUL() argument
3597 return canCombine(MBB, MO, MulOpc); in canCombineWithFMUL()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 3119 unsigned MulOpc = Signed ? AMDGPUISD::MUL_I24 : AMDGPUISD::MUL_U24; in getMul24() local
3120 return DAG.getNode(MulOpc, SL, MVT::i32, N0, N1); in getMul24()
3127 unsigned MulOpc = Signed ? AMDGPUISD::MUL_LOHI_I24 : AMDGPUISD::MUL_LOHI_U24; in getMul24() local
3129 SDValue Mul = DAG.getNode(MulOpc, SL, in getMul24()
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