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Searched refs:NEG (Results 1 – 25 of 162) sorted by relevance

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/external/llvm/test/Transforms/InstCombine/
D	abs_abs.ll	13 ; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x 14 ; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 %x, i32 [[NEG]] 28 ; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x 29 ; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 %x, i32 [[NEG]] 43 ; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x 44 ; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[NEG]], i32 %x 58 ; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x 59 ; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[NEG]], i32 %x 73 ; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x 74 ; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 %x, i32 [[NEG]] [all …]
D	abs-1.ll	`17 ; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub i32 0, %x 18 ; CHECK-NEXT: [[RET:%[a-z0-9]+]] = select i1 [[ISPOS]], i32 %x, i32 [[NEG]] 27 ; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub i64 0, %x 28 ; CHECK-NEXT: [[RET:%[a-z0-9]+]] = select i1 [[ISPOS]], i64 %x, i64 [[NEG]] 37 ; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub i64 0, %x 38 ; CHECK-NEXT: [[RET:%[a-z0-9]+]] = select i1 [[ISPOS]], i64 %x, i64 [[NEG]]`
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
D	ds-sub-offset.ll	26 ; CI-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SCALED]] 27 ; GFX9-DAG: v_sub_u32_e32 [[NEG:v[0-9]+]], 0, [[SCALED]] 29 ; GCN: ds_write_b8 [[NEG]], [[K]] offset:65535 42 ; CI-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0x10000, [[SCALED]] 43 ; GFX9-DAG: v_sub_u32_e32 [[NEG:v[0-9]+]], 0x10000, [[SCALED]] 45 ; GCN: ds_write_b8 [[NEG]], [[K]]{{$}} 58 ; CI-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SCALED]] 59 ; GFX9-DAG: v_sub_u32_e32 [[NEG:v[0-9]+]], 0, [[SCALED]] 62 ; GCN: ds_write_b32 [[NEG]], [[K]] offset:123{{$}} 64 ; GCN: ds_write_b32 [[NEG]], [[K]] offset:456{{$}} [all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/
D	masked-merge-and-of-ors.ll	19 ; CHECK-NEXT: [[NEG:%.]] = xor i32 [[M:%.]], -1 20 ; CHECK-NEXT: [[OR:%.]] = or i32 [[NEG]], [[X:%.]] 34 ; CHECK-NEXT: [[NEG:%.]] = xor <2 x i32> [[M:%.]], <i32 -1, i32 -1> 35 ; CHECK-NEXT: [[OR:%.]] = or <2 x i32> [[NEG]], [[X:%.]] 49 ; CHECK-NEXT: [[NEG:%.]] = xor <3 x i32> [[M:%.]], <i32 -1, i32 undef, i32 -1> 50 ; CHECK-NEXT: [[OR:%.]] = or <3 x i32> [[NEG]], [[X:%.]] 127 ; CHECK-NEXT: [[NEG:%.]] = xor i32 [[M:%.]], -1 128 ; CHECK-NEXT: [[OR:%.]] = or i32 [[NEG]], [[X:%.]] 143 ; CHECK-NEXT: [[NEG:%.]] = xor i32 [[M:%.]], -1 144 ; CHECK-NEXT: [[OR:%.]] = or i32 [[NEG]], [[X:%.]] [all …]
D	masked-merge-xor.ll	22 ; CHECK-NEXT: [[NEG:%.]] = xor i32 [[M]], -1 23 ; CHECK-NEXT: [[AND1:%.]] = and i32 [[NEG]], [[Y:%.]] 37 ; CHECK-NEXT: [[NEG:%.]] = xor <2 x i32> [[M]], <i32 -1, i32 -1> 38 ; CHECK-NEXT: [[AND1:%.]] = and <2 x i32> [[NEG]], [[Y:%.]] 52 ; CHECK-NEXT: [[NEG:%.]] = xor <3 x i32> [[M]], <i32 -1, i32 undef, i32 -1> 53 ; CHECK-NEXT: [[AND1:%.]] = and <3 x i32> [[NEG]], [[Y:%.]] 186 ; CHECK-NEXT: [[NEG:%.]] = xor i32 [[M]], -1 187 ; CHECK-NEXT: [[AND1:%.]] = and i32 [[NEG]], [[Y:%.]] 202 ; CHECK-NEXT: [[NEG:%.]] = xor i32 [[M]], -1 203 ; CHECK-NEXT: [[AND1:%.]] = and i32 [[Y]], [[NEG]] [all …]
D	masked-merge-add.ll	22 ; CHECK-NEXT: [[NEG:%.]] = xor i32 [[M]], -1 23 ; CHECK-NEXT: [[AND1:%.]] = and i32 [[NEG]], [[Y:%.]] 37 ; CHECK-NEXT: [[NEG:%.]] = xor <2 x i32> [[M]], <i32 -1, i32 -1> 38 ; CHECK-NEXT: [[AND1:%.]] = and <2 x i32> [[NEG]], [[Y:%.]] 52 ; CHECK-NEXT: [[NEG:%.]] = xor <3 x i32> [[M]], <i32 -1, i32 undef, i32 -1> 53 ; CHECK-NEXT: [[AND1:%.]] = and <3 x i32> [[NEG]], [[Y:%.]] 186 ; CHECK-NEXT: [[NEG:%.]] = xor i32 [[M]], -1 187 ; CHECK-NEXT: [[AND1:%.]] = and i32 [[NEG]], [[Y:%.]] 202 ; CHECK-NEXT: [[NEG:%.]] = xor i32 [[M]], -1 203 ; CHECK-NEXT: [[AND1:%.]] = and i32 [[Y]], [[NEG]] [all …]
D	masked-merge-or.ll	22 ; CHECK-NEXT: [[NEG:%.]] = xor i32 [[M]], -1 23 ; CHECK-NEXT: [[AND1:%.]] = and i32 [[NEG]], [[Y:%.]] 37 ; CHECK-NEXT: [[NEG:%.]] = xor <2 x i32> [[M]], <i32 -1, i32 -1> 38 ; CHECK-NEXT: [[AND1:%.]] = and <2 x i32> [[NEG]], [[Y:%.]] 52 ; CHECK-NEXT: [[NEG:%.]] = xor <3 x i32> [[M]], <i32 -1, i32 undef, i32 -1> 53 ; CHECK-NEXT: [[AND1:%.]] = and <3 x i32> [[NEG]], [[Y:%.]] 186 ; CHECK-NEXT: [[NEG:%.]] = xor i32 [[M]], -1 187 ; CHECK-NEXT: [[AND1:%.]] = and i32 [[NEG]], [[Y:%.]] 202 ; CHECK-NEXT: [[NEG:%.]] = xor i32 [[M]], -1 203 ; CHECK-NEXT: [[AND1:%.]] = and i32 [[Y]], [[NEG]] [all …]
D	abs-1.ll	16 ; CHECK-NEXT: [[NEG:%.]] = sub nsw i32 0, [[X]] 17 ; CHECK-NEXT: [[TMP2:%.]] = select i1 [[TMP1]], i32 [[NEG]], i32 [[X]] 27 ; CHECK-NEXT: [[NEG:%.]] = sub nsw i64 0, [[X]] 28 ; CHECK-NEXT: [[TMP2:%.]] = select i1 [[TMP1]], i64 [[NEG]], i64 [[X]] 38 ; CHECK-NEXT: [[NEG:%.]] = sub nsw i64 0, [[X]] 39 ; CHECK-NEXT: [[TMP2:%.]] = select i1 [[TMP1]], i64 [[NEG]], i64 [[X]] 51 ; CHECK-NEXT: [[NEG:%.]] = sub i8 0, [[X]] 52 ; CHECK-NEXT: [[ABS:%.]] = select i1 [[CMP]], i8 [[NEG]], i8 [[X]] 66 ; CHECK-NEXT: [[NEG:%.]] = sub <2 x i8> zeroinitializer, [[X]] 67 ; CHECK-NEXT: [[ABS:%.]] = select <2 x i1> [[CMP]], <2 x i8> [[NEG]], <2 x i8> [[X]] [all …]
D	call-callconv.ll	`10 ; CHECK-NEXT: [[NEG:%.]] = sub nsw i32 0, [[I]] 11 ; CHECK-NEXT: [[TMP2:%.]] = select i1 [[TMP1]], i32 [[NEG]], i32 [[I]] 23 ; CHECK-NEXT: [[NEG:%.]] = sub nsw i32 0, [[I]] 24 ; CHECK-NEXT: [[TMP2:%.]] = select i1 [[TMP1]], i32 [[NEG]], i32 [[I]]`
D	rotate.ll	`134 ; CHECK-NEXT: [[NEG:%.]] = sub i16 0, [[SHAMT]] 135 ; CHECK-NEXT: [[LSHAMT:%.]] = and i16 [[NEG]], 15 161 ; CHECK-NEXT: [[NEG:%.]] = sub i8 0, [[SHAMT]] 162 ; CHECK-NEXT: [[LSHAMT:%.]] = and i8 [[NEG]], 7 191 ; CHECK-NEXT: [[NEG:%.]] = sub i32 0, [[SHAMT]] 192 ; CHECK-NEXT: [[LSHAMT:%.]] = and i32 [[NEG]], 15 214 ; CHECK-NEXT: [[NEG:%.]] = sub i32 0, [[SHAMT]] 215 ; CHECK-NEXT: [[LSHAMT:%.]] = and i32 [[NEG]], 7`
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/
D	atomicrmw-sub-06.ll	`8 ; CHECK: lcgr [[NEG:%r[0-5]]], %r4 9 ; CHECK: laag %r2, [[NEG]], 0(%r3) 28 ; CHECK: lcgr [[NEG:%r[0-5]]], %r4 29 ; CHECK: laag %r2, [[NEG]], 524280(%r3) 39 ; CHECK-DAG: lcgr [[NEG:%r[0-5]]], %r4 41 ; CHECK: laag %r2, [[NEG]], 0(%r3) 51 ; CHECK: lcgr [[NEG:%r[0-5]]], %r4 52 ; CHECK: laag %r2, [[NEG]], -524288(%r3) 62 ; CHECK-DAG: lcgr [[NEG:%r[0-5]]], %r4 64 ; CHECK: laag %r2, [[NEG]], 0(%r3)`
D	atomicrmw-sub-05.ll	`8 ; CHECK: lcr [[NEG:%r[0-5]]], %r4 9 ; CHECK: laa %r2, [[NEG]], 0(%r3) 28 ; CHECK: lcr [[NEG:%r[0-5]]], %r4 29 ; CHECK: laa %r2, [[NEG]], 524284(%r3) 39 ; CHECK-DAG: lcr [[NEG:%r[0-5]]], %r4 41 ; CHECK: laa %r2, [[NEG]], 0(%r3) 51 ; CHECK: lcr [[NEG:%r[0-5]]], %r4 52 ; CHECK: laa %r2, [[NEG]], -524288(%r3) 62 ; CHECK-DAG: lcr [[NEG:%r[0-5]]], %r4 64 ; CHECK: laa %r2, [[NEG]], 0(%r3)`
/external/llvm/test/CodeGen/SystemZ/
D	atomicrmw-sub-05.ll	`8 ; CHECK: lcr [[NEG:%r[0-5]]], %r4 9 ; CHECK: laa %r2, [[NEG]], 0(%r3) 28 ; CHECK: lcr [[NEG:%r[0-5]]], %r4 29 ; CHECK: laa %r2, [[NEG]], 524284(%r3) 39 ; CHECK-DAG: lcr [[NEG:%r[0-5]]], %r4 41 ; CHECK: laa %r2, [[NEG]], 0(%r3) 51 ; CHECK: lcr [[NEG:%r[0-5]]], %r4 52 ; CHECK: laa %r2, [[NEG]], -524288(%r3) 62 ; CHECK-DAG: lcr [[NEG:%r[0-5]]], %r4 64 ; CHECK: laa %r2, [[NEG]], 0(%r3)`
D	atomicrmw-sub-06.ll	`8 ; CHECK: lcgr [[NEG:%r[0-5]]], %r4 9 ; CHECK: laag %r2, [[NEG]], 0(%r3) 28 ; CHECK: lcgr [[NEG:%r[0-5]]], %r4 29 ; CHECK: laag %r2, [[NEG]], 524280(%r3) 39 ; CHECK-DAG: lcgr [[NEG:%r[0-5]]], %r4 41 ; CHECK: laag %r2, [[NEG]], 0(%r3) 51 ; CHECK: lcgr [[NEG:%r[0-5]]], %r4 52 ; CHECK: laag %r2, [[NEG]], -524288(%r3) 62 ; CHECK-DAG: lcgr [[NEG:%r[0-5]]], %r4 64 ; CHECK: laag %r2, [[NEG]], 0(%r3)`
/external/llvm/test/CodeGen/AMDGPU/
D	ds-sub-offset.ll	24 ; GCN-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SCALED]] 26 ; GCN: ds_write_b8 [[NEG]], [[K]] offset:65535 39 ; GCN-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0x10000, [[SCALED]] 41 ; GCN: ds_write_b8 [[NEG]], [[K]]{{$}} 54 ; GCN-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SCALED]] 57 ; GCN: ds_write_b32 [[NEG]], [[K]] offset:123{{$}} 59 ; GCN: ds_write_b32 [[NEG]], [[K]] offset:456{{$}} 76 ; GCN-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SCALED]] 79 ; GCN: ds_write_b32 [[NEG]], [[K]] offset:123{{$}} 81 ; GCN: ds_write_b32 [[NEG]], [[K]] offset:123{{$}} [all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/
D	sr1.ll	`3 …nux-gnu -march=mipsel -mattr=mips16 -relocation-model=static < %s \| FileCheck %s -check-prefix=NEG 49 ; NEG: .ent foo3 50 ; NEG-NOT: save $16, $17, $ra, $18, [[FS:[0-9]+]] # 16 bit inst 51 ; NEG-NOT: restore $16, $17, $ra, $18, [[FS]] # 16 bit inst 52 ; NEG: .end foo3`
/external/llvm/test/CodeGen/Mips/
D	sr1.ll	`3 …nux-gnu -march=mipsel -mattr=mips16 -relocation-model=static < %s \| FileCheck %s -check-prefix=NEG 49 ; NEG: .ent foo3 50 ; NEG-NOT: save $16, $17, $ra, $18, [[FS:[0-9]+]] # 16 bit inst 51 ; NEG-NOT: restore $16, $17, $ra, $18, [[FS]] # 16 bit inst 52 ; NEG: .end foo3`
/external/libyuv/files/unit_test/
D	convert_test.cc	34 FMT_PLANAR, SUBSAMP_X, SUBSAMP_Y, W1280, N, NEG, OFF) \ argument 81 SUBSAMPLE(kWidth, SUBSAMP_X), kWidth, NEG kHeight); \ 88 SUBSAMPLE(kWidth, SUBSAMP_X), kWidth, NEG kHeight); \ 159 W1280, N, NEG, OFF, PN, OFF_U, OFF_V) \ argument 207 SUBSAMPLE(kWidth, SUBSAMP_X), kWidth, NEG kHeight); \ 214 dst_v_opt, SUBSAMPLE(kWidth, SUBSAMP_X), kWidth, NEG kHeight); \ 282 FMT_PLANAR, SUBSAMP_X, SUBSAMP_Y, W1280, N, NEG, OFF) \ argument 320 dst_uv_c, SUBSAMPLE(kWidth * 2, SUBSAMP_X), kWidth, NEG kHeight); \ 326 dst_uv_opt, SUBSAMPLE(kWidth * 2, SUBSAMP_X), kWidth, NEG kHeight); \ 376 FMT_PLANAR, SUBSAMP_X, SUBSAMP_Y, W1280, N, NEG, OFF, \ argument [all …]
/external/llvm/test/Transforms/InstSimplify/
D	call-callconv.ll	`11 ; CHECK: %[[NEG:.]] = sub i32 0, %i 12 ; CHECK: %[[RET:.]] = select i1 %[[ISPOS]], i32 %i, i32 %[[NEG]] 23 ; CHECK: %[[NEG:.]] = sub i32 0, %i 24 ; CHECK: %[[RET:.]] = select i1 %[[ISPOS]], i32 %i, i32 %[[NEG]]`
/external/dtc/tests/
D	dtc-fails.sh	`6 NEG="$1" 18 if [ -n "$NEG" ]; then`
/external/libxaac/decoder/armv8/
D	ixheaacd_post_twiddle.s	`170 NEG v28.4s, v28.4s 215 NEG v22.4s, v22.4s 241 NEG v0.4s, v0.4s 261 NEG v16.4s, v6.4s 297 NEG v28.4s, v28.4s 344 NEG v22.4s, v22.4s 369 NEG v0.4s, v0.4s 390 NEG v16.4s, v6.4s 434 NEG v28.4s, v28.4s 479 NEG v22.4s, v22.4s [all …]`
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/Util/
D	strip-nonlinetable-debuginfo-containingtypes.ll	`3 ; RUN: cat %t.ll \| FileCheck %s --check-prefix=CHECK-NEG 52 ; CHECK-NEG-NOT: !DI{{Basic\|Composite\|Derived}}Type 80 ; CHECK-NEG-NOT: !DISubprogram(name: "~A" 94 ; CHECK-NEG-NOT: !DISubprogram(name: "B", {{.*}}, isDefinition: false`
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/NewGVN/
D	pr35125.ll	`10 ; CHECK-NEXT: [[NEG:%.]] = xor i32 [[TMP0]], -1 16 ; CHECK-NEXT: [[PHIOFOPS:%.]] = phi i32 [ [[TMP0]], [[ENTRY:%.]] ], [ [[NEG]], [[IF_THEN]] ] 17 ; CHECK-NEXT: [[STOREMERGE:%.]] = phi i32 [ [[TMP0]], [[IF_THEN]] ], [ [[NEG]], [[ENTRY]] ]`
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/EarlyCSE/
D	commute.ll	`223 ; CHECK-NEXT: [[NEG:%.]] = sub i8 0, %a 226 ; CHECK-NEXT: [[M1:%.]] = select i1 [[CMP1]], i8 %a, i8 [[NEG]] 240 ; CHECK-NEXT: [[NEG:%.]] = sub i8 0, %a 243 ; CHECK-NEXT: [[M1:%.]] = select i1 [[CMP1]], i8 %a, i8 [[NEG]] 259 ; CHECK-NEXT: [[NEG:%.]] = sub i8 0, %a 262 ; CHECK-NEXT: [[M1:%.]] = select i1 [[CMP1]], i8 %a, i8 [[NEG]] 276 ; CHECK-NEXT: [[NEG:%.]] = sub i8 0, %a 279 ; CHECK-NEXT: [[M1:%.]] = select i1 [[CMP1]], i8 %a, i8 [[NEG]]`
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/IndVarSimplify/
D	pr32045.ll	`12 ; CHECK-NEXT: [[NEG:%.]] = xor i32 [[SHR1]], -1 13 ; CHECK-NEXT: store i32 [[NEG]], i32 %sink`

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