Searched refs:NO_STACK_SLOT (Results 1 – 18 of 18) sorted by relevance
62 LowSpillSlot = HighSpillSlot = NO_STACK_SLOT; in runOnMachineFunction()106 if (LowSpillSlot == NO_STACK_SLOT) in createSpillSlot()108 if (HighSpillSlot == NO_STACK_SLOT || SS > HighSpillSlot) in createSpillSlot()131 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && in assignVirt2StackSlot()139 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && in assignVirt2StackSlot()149 assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT && in assignVirtReMatId()157 assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT && in assignVirtReMatId()371 if (Virt2StackSlotMap[Reg] != VirtRegMap::NO_STACK_SLOT) { in print()
44 NO_STACK_SLOT = (1L << 30)-1, enumerator147 Virt2StackSlotMap(NO_STACK_SLOT), in VirtRegMap()148 Virt2ReMatIdMap(NO_STACK_SLOT), Virt2SplitMap(0), in VirtRegMap()151 LowSpillSlot(NO_STACK_SLOT), HighSpillSlot(NO_STACK_SLOT) { } in VirtRegMap()238 if (getStackSlot(virtReg) == NO_STACK_SLOT && in isAssignedReg()239 getReMatId(virtReg) == NO_STACK_SLOT) in isAssignedReg()
220 if (SS == VirtRegMap::NO_STACK_SLOT) in spill()
583 (vrm->getStackSlot(li->reg) == VirtRegMap::NO_STACK_SLOT)) { in getLiveStateAt()595 (vrm->getStackSlot(li->reg) == VirtRegMap::NO_STACK_SLOT)) { in getLiveStateAt()
1248 int LastReloadSS = VirtRegMap::NO_STACK_SLOT; in assignRegOrStackSlotAtInterval()1395 int LastReloadSS = VirtRegMap::NO_STACK_SLOT; in assignRegOrStackSlotAtInterval()
1339 vrm.getStackSlot(NewVReg) == VirtRegMap::NO_STACK_SLOT) { in rewriteInstructionForSpills()1342 assert(Slot != VirtRegMap::NO_STACK_SLOT); in rewriteInstructionForSpills()1862 if (vrm.getStackSlot(li.reg) == VirtRegMap::NO_STACK_SLOT) in addIntervalsForSpills()
495 if (stackSlot == VirtRegMap::NO_STACK_SLOT) { in addStackInterval()
1243 if (SS != VirtRegMap::NO_STACK_SLOT) { in runOnMachineFunction()1387 int FoldedSS = VirtRegMap::NO_STACK_SLOT; in OptimizeByUnfold()2346 if (SS == VirtRegMap::NO_STACK_SLOT) in RewriteMBB()
892 } else if (VRM.getStackSlot(VirtReg) != VirtRegMap::NO_STACK_SLOT && in rewriteLocations()
1208 if (StackSlot == VirtRegMap::NO_STACK_SLOT) { in spillAll()
38 NO_STACK_SLOT = (1L << 30)-1, enumerator72 Virt2StackSlotMap(NO_STACK_SLOT), Virt2SplitMap(0) {} in VirtRegMap()155 if (getStackSlot(virtReg) == NO_STACK_SLOT) in isAssignedReg()
36 NO_STACK_SLOT = (1L << 30)-1, enumerator72 Virt2StackSlotMap(NO_STACK_SLOT), Virt2SplitMap(0) { } in VirtRegMap()159 if (getStackSlot(virtReg) == NO_STACK_SLOT) in isAssignedReg()
102 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && in assignVirt2StackSlot()110 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && in assignVirt2StackSlot()131 if (Virt2StackSlotMap[Reg] != VirtRegMap::NO_STACK_SLOT) { in print()
976 if (StackSlot == VirtRegMap::NO_STACK_SLOT) { in spillAll()1374 if (Slot != VirtRegMap::NO_STACK_SLOT) in hoistAllSpills()1452 else if (VRM.getStackSlot(Old) != VirtRegMap::NO_STACK_SLOT) in LRE_DidCloneVirtReg()
930 } else if (VRM.getStackSlot(VirtReg) != VirtRegMap::NO_STACK_SLOT) { in rewriteLocations()
123 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && in assignVirt2StackSlot()131 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && in assignVirt2StackSlot()152 if (Virt2StackSlotMap[Reg] != VirtRegMap::NO_STACK_SLOT) { in print()
1031 if (StackSlot == VirtRegMap::NO_STACK_SLOT) { in spillAll()1502 else if (VRM.getStackSlot(Old) != VirtRegMap::NO_STACK_SLOT) in LRE_DidCloneVirtReg()
1067 } else if (VRM.getStackSlot(VirtReg) != VirtRegMap::NO_STACK_SLOT) { in rewriteLocations()