Searched refs:NUM_OF_CS (Results 1 – 3 of 3) sorted by relevance
43 for (c_cs = 0; c_cs < NUM_OF_CS; c_cs++) { in ddr3_tip_max_cs_get()71 u8 rl_values[NUM_OF_CS][MAX_BUS_NUM][MAX_INTERFACE_NUM]; in ddr3_tip_dynamic_read_leveling()77 for (effective_cs = 0; effective_cs < NUM_OF_CS; effective_cs++) in ddr3_tip_dynamic_read_leveling()842 u8 wl_values[NUM_OF_CS][MAX_BUS_NUM][MAX_INTERFACE_NUM]; in ddr3_tip_dynamic_write_leveling()1699 enum rl_dqs_burst_state rl_state[NUM_OF_CS][MAX_BUS_NUM][MAX_INTERFACE_NUM] = { { {0} } }; in mv_ddr_rl_dqs_burst()1711 u32 rl_values[NUM_OF_CS][MAX_BUS_NUM][MAX_INTERFACE_NUM] = { { {0} } }; in mv_ddr_rl_dqs_burst()1712 u32 rl_min_values[NUM_OF_CS][MAX_BUS_NUM][MAX_INTERFACE_NUM] = { { {0} } }; in mv_ddr_rl_dqs_burst()1713 u32 rl_max_values[NUM_OF_CS][MAX_BUS_NUM][MAX_INTERFACE_NUM] = { { {0} } }; in mv_ddr_rl_dqs_burst()1714 u32 rl_val, rl_min_val[NUM_OF_CS], rl_max_val[NUM_OF_CS]; in mv_ddr_rl_dqs_burst()
74 #define NUM_OF_CS 4 macro
511 for (cs_cnt = 0; cs_cnt < NUM_OF_CS; cs_cnt++) { in hws_ddr3_tip_init_controller()