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1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2010-2015
4  * NVIDIA Corporation <www.nvidia.com>
5  */
6 
7 #ifndef _TEGRA_H_
8 #define _TEGRA_H_
9 
10 #define NV_PA_ARM_PERIPHBASE	0x50040000
11 #define NV_PA_PG_UP_BASE	0x60000000
12 #define NV_PA_TMRUS_BASE	0x60005010
13 #define NV_PA_CLK_RST_BASE	0x60006000
14 #define NV_PA_FLOW_BASE		0x60007000
15 #define NV_PA_GPIO_BASE		0x6000D000
16 #define NV_PA_EVP_BASE		0x6000F000
17 #define NV_PA_APB_MISC_BASE	0x70000000
18 #define NV_PA_APB_MISC_GP_BASE	(NV_PA_APB_MISC_BASE + 0x0800)
19 #define NV_PA_APB_UARTA_BASE	(NV_PA_APB_MISC_BASE + 0x6000)
20 #define NV_PA_APB_UARTB_BASE	(NV_PA_APB_MISC_BASE + 0x6040)
21 #define NV_PA_APB_UARTC_BASE	(NV_PA_APB_MISC_BASE + 0x6200)
22 #define NV_PA_APB_UARTD_BASE	(NV_PA_APB_MISC_BASE + 0x6300)
23 #define NV_PA_APB_UARTE_BASE	(NV_PA_APB_MISC_BASE + 0x6400)
24 #define NV_PA_NAND_BASE		(NV_PA_APB_MISC_BASE + 0x8000)
25 #define NV_PA_SPI_BASE		(NV_PA_APB_MISC_BASE + 0xC380)
26 #define NV_PA_SLINK1_BASE	(NV_PA_APB_MISC_BASE + 0xD400)
27 #define NV_PA_SLINK2_BASE	(NV_PA_APB_MISC_BASE + 0xD600)
28 #define NV_PA_SLINK3_BASE	(NV_PA_APB_MISC_BASE + 0xD800)
29 #define NV_PA_SLINK4_BASE	(NV_PA_APB_MISC_BASE + 0xDA00)
30 #define NV_PA_SLINK5_BASE	(NV_PA_APB_MISC_BASE + 0xDC00)
31 #define NV_PA_SLINK6_BASE	(NV_PA_APB_MISC_BASE + 0xDE00)
32 #define TEGRA_DVC_BASE		(NV_PA_APB_MISC_BASE + 0xD000)
33 #define NV_PA_PMC_BASE		(NV_PA_APB_MISC_BASE + 0xE400)
34 #define NV_PA_EMC_BASE		(NV_PA_APB_MISC_BASE + 0xF400)
35 #define NV_PA_FUSE_BASE		(NV_PA_APB_MISC_BASE + 0xF800)
36 #if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \
37 	defined(CONFIG_TEGRA114)
38 #define NV_PA_CSITE_BASE	0x70040000
39 #else
40 #define NV_PA_CSITE_BASE	0x70800000
41 #endif
42 #define TEGRA_USB_ADDR_MASK	0xFFFFC000
43 
44 #define NV_PA_SDRC_CS0		NV_PA_SDRAM_BASE
45 #define LOW_LEVEL_SRAM_STACK	0x4000FFFC
46 #define EARLY_AVP_STACK		(NV_PA_SDRAM_BASE + 0x20000)
47 #define EARLY_CPU_STACK		(EARLY_AVP_STACK - 4096)
48 #define PG_UP_TAG_AVP		0xAAAAAAAA
49 
50 #ifndef __ASSEMBLY__
51 struct timerus {
52 	unsigned int cntr_1us;
53 };
54 
55 /* Address at which WB code runs, it must not overlap Bootrom's IRAM usage */
56 #define NV_WB_RUN_ADDRESS	0x40020000
57 
58 #define NVBOOTTYPE_RECOVERY	2	/* BR entered RCM */
59 #define NVBOOTINFOTABLE_BOOTTYPE 0xC	/* Boot type in BIT in IRAM */
60 #define NVBOOTINFOTABLE_BCTSIZE	0x38	/* BCT size in BIT in IRAM */
61 #define NVBOOTINFOTABLE_BCTPTR	0x3C	/* BCT pointer in BIT in IRAM */
62 
63 /* These are the available SKUs (product types) for Tegra */
64 enum {
65 	SKU_ID_T20_7		= 0x7,
66 	SKU_ID_T20		= 0x8,
67 	SKU_ID_T25SE		= 0x14,
68 	SKU_ID_AP25		= 0x17,
69 	SKU_ID_T25		= 0x18,
70 	SKU_ID_AP25E		= 0x1b,
71 	SKU_ID_T25E		= 0x1c,
72 	SKU_ID_T33		= 0x80,
73 	SKU_ID_T30		= 0x81, /* Cardhu value */
74 	SKU_ID_TM30MQS_P_A3	= 0xb1,
75 	SKU_ID_T114_ENG		= 0x00, /* Dalmore value, unfused */
76 	SKU_ID_T114_1		= 0x01,
77 	SKU_ID_T124_ENG		= 0x00, /* Venice2 value, unfused */
78 	SKU_ID_T210_ENG		= 0x00, /* unfused value TBD */
79 };
80 
81 /*
82  * These are used to distinguish SOC types for setting up clocks. Mostly
83  * we can tell the clocking required by looking at the SOC sku_id, but
84  * for T30 it is a user option as to whether to run PLLP in fast or slow
85  * mode, so we have two options there.
86  */
87 enum {
88 	TEGRA_SOC_T20,
89 	TEGRA_SOC_T25,
90 	TEGRA_SOC_T30,
91 	TEGRA_SOC_T114,
92 	TEGRA_SOC_T124,
93 	TEGRA_SOC_T210,
94 
95 	TEGRA_SOC_CNT,
96 	TEGRA_SOC_UNKNOWN	= -1,
97 };
98 
99 /* Tegra system controller (SYSCON) devices */
100 enum {
101 	TEGRA_SYSCON_PMC,
102 };
103 
104 #else  /* __ASSEMBLY__ */
105 #define PRM_RSTCTRL		NV_PA_PMC_BASE
106 #endif
107 
108 #endif	/* TEGRA_H */
109