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Searched refs:NV_PA_CLK_RST_BASE (Results 1 – 15 of 15) sorted by relevance

/external/u-boot/arch/arm/mach-tegra/tegra20/
Dclock.c395 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; in clock_get_osc_freq()
406 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; in get_periph_source_reg()
510 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; in clock_set_enable()
527 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; in reset_set_enable()
661 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); in tegra_plle_train()
683 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); in tegra_plle_enable()
686 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); in tegra_plle_enable()
689 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); in tegra_plle_enable()
693 writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC); in tegra_plle_enable()
695 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); in tegra_plle_enable()
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Dwarmboot_avp.c29 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; in wb_start()
/external/u-boot/arch/arm/mach-tegra/tegra30/
Dclock.c445 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; in clock_get_osc_freq()
461 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; in get_periph_source_reg()
557 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; in clock_set_enable()
578 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; in reset_set_enable()
690 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); in tegra_plle_train()
712 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); in tegra_plle_enable()
715 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); in tegra_plle_enable()
718 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); in tegra_plle_enable()
722 writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC); in tegra_plle_enable()
724 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); in tegra_plle_enable()
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Dcpu.c87 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; in t30_init_clocks()
/external/u-boot/arch/arm/mach-tegra/tegra210/
Dclock.c676 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; in clock_get_osc_freq()
702 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; in get_periph_source_reg()
813 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; in clock_set_enable()
839 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; in reset_set_enable()
936 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; in tegra210_setup_pllp()
972 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; in clock_early_init()
1035 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; in clk_m_get_rate()
1089 value = readl(NV_PA_CLK_RST_BASE + PLLREFE_MISC); in tegra_pllref_enable()
1091 writel(value, NV_PA_CLK_RST_BASE + PLLREFE_MISC); in tegra_pllref_enable()
1100 writel(value, NV_PA_CLK_RST_BASE + PLLREFE_BASE); in tegra_pllref_enable()
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Dxusb-padctl.c369 value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0); in pcie_phy_enable()
374 writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0); in pcie_phy_enable()
390 value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0); in pcie_phy_enable()
392 writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0); in pcie_phy_enable()
/external/u-boot/arch/arm/mach-tegra/tegra124/
Dclock.c607 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; in clock_get_osc_freq()
623 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; in get_periph_source_reg()
723 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; in clock_set_enable()
746 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; in reset_set_enable()
837 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; in clock_early_init()
903 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; in clock_early_init_done()
966 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); in tegra_plle_enable()
968 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); in tegra_plle_enable()
970 value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX); in tegra_plle_enable()
973 writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX); in tegra_plle_enable()
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Dcpu.c46 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; in enable_cpu_clocks()
83 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; in remove_cpu_resets()
116 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; in tegra124_init_clocks()
/external/u-boot/arch/arm/mach-tegra/tegra114/
Dcpu.c21 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; in enable_cpu_power_rail()
53 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; in enable_cpu_clocks()
78 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; in remove_cpu_resets()
111 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; in t114_init_clocks()
Dclock.c465 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; in clock_get_osc_freq()
481 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; in get_periph_source_reg()
577 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; in clock_set_enable()
598 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; in reset_set_enable()
657 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; in clock_early_init()
/external/u-boot/arch/arm/mach-tegra/
Dcpu.c156 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; in pllx_set_iddq()
230 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; in init_pllx()
260 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; in enable_cpu_clock()
Dclock.c63 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; in clock_get_osc_bypass()
74 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; in get_pll()
513 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; in reset_cmplx_set_enable()
725 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; in set_avp_clock_source()
744 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; in tegra30_set_up_pllp()
/external/u-boot/arch/arm/include/asm/arch-tegra/
Dtegra.h13 #define NV_PA_CLK_RST_BASE 0x60006000 macro
/external/u-boot/drivers/pci/
Dpci_tegra.c638 value = readl(NV_PA_CLK_RST_BASE + 0x48c); in tegra_pcie_power_on()
641 writel(value, NV_PA_CLK_RST_BASE + 0x48c); in tegra_pcie_power_on()
/external/u-boot/drivers/usb/host/
Dehci-tegra.c409 clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; in init_utmi_usb_controller()