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Searched refs:NV_PA_CSITE_BASE (Results 1 – 3 of 3) sorted by relevance

/external/u-boot/arch/arm/mach-tegra/
Dcpu.h40 #define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0)
41 #define CSITE_CPU_DBG1_LAR (NV_PA_CSITE_BASE + 0x12FB0)
42 #define CSITE_CPU_DBG2_LAR (NV_PA_CSITE_BASE + 0x14FB0)
43 #define CSITE_CPU_DBG3_LAR (NV_PA_CSITE_BASE + 0x16FB0)
/external/u-boot/arch/arm/include/asm/arch-tegra/
Dap.h30 #define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0)
31 #define CSITE_CPU_DBG1_LAR (NV_PA_CSITE_BASE + 0x12FB0)
Dtegra.h38 #define NV_PA_CSITE_BASE 0x70040000 macro
40 #define NV_PA_CSITE_BASE 0x70800000 macro