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Searched refs:NV_PA_SDRAM_BASE (Results 1 – 10 of 10) sorted by relevance

/external/u-boot/arch/arm/include/asm/arch-tegra/
Dtegra.h44 #define NV_PA_SDRC_CS0 NV_PA_SDRAM_BASE
46 #define EARLY_AVP_STACK (NV_PA_SDRAM_BASE + 0x20000)
/external/u-boot/arch/arm/include/asm/arch-tegra186/
Dtegra.h11 #define NV_PA_SDRAM_BASE 0x80000000 macro
/external/u-boot/arch/arm/include/asm/arch-tegra20/
Dtegra.h10 #define NV_PA_SDRAM_BASE 0x00000000 macro
/external/u-boot/arch/arm/include/asm/arch-tegra30/
Dtegra.h10 #define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T30 */ macro
/external/u-boot/arch/arm/include/asm/arch-tegra114/
Dtegra.h9 #define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T114 */ macro
/external/u-boot/arch/arm/include/asm/arch-tegra124/
Dtegra.h10 #define NV_PA_SDRAM_BASE 0x80000000 macro
/external/u-boot/arch/arm/include/asm/arch-tegra210/
Dtegra.h15 #define NV_PA_SDRAM_BASE 0x80000000 macro
/external/u-boot/arch/arm/mach-tegra/tegra20/
Dwarmboot.c314 if (seg_length == 0 || seg_address < NV_PA_SDRAM_BASE || in warmboot_prepare_code()
315 seg_address + seg_length >= NV_PA_SDRAM_BASE + gd->ram_size) { in warmboot_prepare_code()
/external/u-boot/arch/arm/mach-tegra/
Dboard2.c129 gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100); in board_init()
/external/u-boot/drivers/pci/
Dpci_tegra.c857 afi_writel(pcie, NV_PA_SDRAM_BASE, AFI_CACHE_BAR0_ST);