Searched refs:NeedAlign (Results 1 – 6 of 6) sorted by relevance
385 unsigned NeedAlign = RC->getAlignment(); in scavengeRegister() local398 if (NeedSize > S || NeedAlign > A) in scavengeRegister()406 unsigned D = (S-NeedSize) + (A-NeedAlign); in scavengeRegister()
1561 unsigned NeedAlign = RC->getAlignment(); in expandStoreVec2() local1566 if (NeedAlign <= HasAlign) in expandStoreVec2()1578 if (NeedAlign <= MinAlign(HasAlign, Size)) in expandStoreVec2()1614 unsigned NeedAlign = RC->getAlignment(); in expandLoadVec2() local1619 if (NeedAlign <= HasAlign) in expandLoadVec2()1630 if (NeedAlign <= MinAlign(HasAlign, Size)) in expandLoadVec2()1663 unsigned NeedAlign = RC->getAlignment(); in expandStoreVec() local1667 if (NeedAlign <= HasAlign) in expandStoreVec()1700 unsigned NeedAlign = RC->getAlignment(); in expandLoadVec() local1704 if (NeedAlign <= HasAlign) in expandLoadVec()
1725 unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass); in expandStoreVec2() local1731 StoreOpc = NeedAlign <= HasAlign ? Hexagon::V6_vS32b_ai in expandStoreVec2()1742 StoreOpc = NeedAlign <= MinAlign(HasAlign, Size) ? Hexagon::V6_vS32b_ai in expandStoreVec2()1772 unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass); in expandLoadVec2() local1777 LoadOpc = NeedAlign <= HasAlign ? Hexagon::V6_vL32b_ai in expandLoadVec2()1785 LoadOpc = NeedAlign <= MinAlign(HasAlign, Size) ? Hexagon::V6_vL32b_ai in expandLoadVec2()1811 unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass); in expandStoreVec() local1813 unsigned StoreOpc = NeedAlign <= HasAlign ? Hexagon::V6_vS32b_ai in expandStoreVec()1839 unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass); in expandLoadVec() local1841 unsigned LoadOpc = NeedAlign <= HasAlign ? Hexagon::V6_vL32b_ai in expandLoadVec()
2651 unsigned NeedAlign = Subtarget.getTypeAlignment(LoadTy); in LowerUnalignedLoad() local2652 if (HaveAlign >= NeedAlign) in LowerUnalignedLoad()2672 if (!DoDefault && 2*HaveAlign == NeedAlign) { in LowerUnalignedLoad()2688 assert(LoadTy.getSizeInBits() == 8*NeedAlign); in LowerUnalignedLoad()2690 unsigned LoadLen = NeedAlign; in LowerUnalignedLoad()2705 DAG.getConstant(NeedAlign, dl, MVT::i32)) in LowerUnalignedLoad()
469 unsigned NeedAlign = TRI->getSpillAlignment(RC); in spill() local482 if (NeedSize > S || NeedAlign > A) in spill()490 unsigned D = (S-NeedSize) + (A-NeedAlign); in spill()
1452 bool NeedAlign; // Does argument declaration specify alignment? in LowerCall() local1461 NeedAlign = true; in LowerCall()1476 NeedAlign = false; in LowerCall()1538 NeedAlign ? GreatestCommonDivisor64(ArgAlign, Offsets[j]) : 0; in LowerCall()