| /external/boringssl/src/crypto/fipsmodule/ec/ |
| D | p256-x86_64_tests.txt | 5 Test = Negate
9 Test = Negate
13 Test = Negate
17 Test = Negate
21 Test = Negate
25 Test = Negate
29 Test = Negate
33 Test = Negate
37 Test = Negate
41 Test = Negate
[all …]
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| /external/tensorflow/tensorflow/compiler/xla/tools/ |
| D | hlo_extractor_test.cc | 46 op::Exp(op::Negate(op::Parameter(0)))); in TEST_F()
60 op::Negate(op::Parameter(0))); in TEST_F()
84 op::Exp(op::Negate(op::Tanh(op::Parameter(0))))); in TEST_F()
97 op::Add(op::Negate(op::Parameter(0)), in TEST_F()
98 op::Exp(op::Negate(op::Parameter(0))))); in TEST_F()
104 op::Add(op::Negate(op::Tanh(op::Parameter(0))), in TEST_F()
105 op::Exp(op::Negate(op::Tanh(op::Parameter(0)))))); in TEST_F()
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| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| D | radeon_optimize.c | 56 combine.Negate = outer.Negate; in chain_srcregs()
59 combine.Negate = swizzle_mask(outer.Swizzle, inner.Negate); in chain_srcregs()
60 combine.Negate ^= outer.Negate; in chain_srcregs()
168 inst->U.I.SrcReg[0].Negate) { in copy_propagate()
214 *pnegate = GET_BIT(src.Negate, chan); in is_src_uniform_constant()
217 if (swz != *pswz || *pnegate != GET_BIT(src.Negate, chan)) { in is_src_uniform_constant()
243 inst->U.I.SrcReg[0].Negate ^= RC_MASK_XYZW; in constant_folding_mad()
257 inst->U.I.SrcReg[1].Negate ^= RC_MASK_XYZW; in constant_folding_mad()
278 inst->U.I.SrcReg[0].Negate ^= RC_MASK_XYZW; in constant_folding_mul()
291 inst->U.I.SrcReg[0].Negate ^= RC_MASK_XYZW; in constant_folding_mul()
[all …]
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| D | radeon_dataflow_swizzles.c | 77 masked_negate = split.Phase[phase] & mov->U.I.SrcReg[0].Negate; in rewrite_source()
79 mov->U.I.SrcReg[0].Negate = 0; in rewrite_source()
81 mov->U.I.SrcReg[0].Negate = RC_MASK_XYZW; in rewrite_source()
88 inst->U.I.SrcReg[src].Negate = RC_MASK_NONE; in rewrite_source()
392 if (reg->Negate & (1 << chan)) { in try_rewrite_constant()
399 if (reg->Negate & (1 << chan)) { in try_rewrite_constant()
407 reg->Swizzle, reg->Negate, chan); in try_rewrite_constant()
418 reg->Negate = 0; in try_rewrite_constant()
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| D | r300_fragprog_swizzle.c | 119 if (reg.Abs || reg.Negate) in r300_swizzle_is_native()
139 if ((reg.Negate & relevant) && ((reg.Negate & relevant) != relevant)) in r300_swizzle_is_native()
175 if (matchmask && (!!(src.Negate & matchmask) != !!(src.Negate & (1 << comp)))) in r300_swizzle_split()
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| D | radeon_pair_translate.c | 47 inst->SrcReg[1].Negate = RC_MASK_NONE; in final_rewrite()
245 …pair->RGB.Arg[i].Negate = !!(srcmask & inst->SrcReg[i].Negate & (RC_MASK_X | RC_MASK_Y | RC_MASK_Z… in set_pair_instruction()
273 pair->Alpha.Arg[i].Negate = in set_pair_instruction()
274 !!(inst->SrcReg[i].Negate & in set_pair_instruction()
277 pair->Alpha.Arg[i].Negate = in set_pair_instruction()
278 !!(inst->SrcReg[i].Negate & RC_MASK_W); in set_pair_instruction()
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| D | r500_fragprog.c | 178 inst_if->U.I.SrcReg[0].Negate = 0; in r500_transform_IF()
197 if (opcode == RC_OPCODE_KIL && (reg.Swizzle != RC_SWIZZLE_XYZW || reg.Negate != RC_MASK_NONE)) in r500_swizzle_is_native()
203 reg.Negate &= ~(1 << i); in r500_swizzle_is_native()
210 if (reg.Negate) in r500_swizzle_is_native()
217 if (reg.Swizzle == RC_SWIZZLE_XYZW && !reg.Abs && !reg.Negate) in r500_swizzle_is_native()
231 if ((reg.Negate & relevant) && ((reg.Negate & relevant) != relevant)) in r500_swizzle_is_native()
254 negatebase[GET_BIT(src.Negate, i)] |= 1 << i; in r500_swizzle_split()
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| D | radeon_program_print.c | 235 int trivial_negate = (src.Negate == RC_MASK_NONE || src.Negate == RC_MASK_XYZW); in rc_print_src_register()
237 if (src.Negate == RC_MASK_XYZW) in rc_print_src_register()
252 rc_print_swizzle(f, src.Swizzle, trivial_negate ? 0 : src.Negate); in rc_print_src_register()
406 const char* neg = inst->RGB.Arg[arg].Negate ? "-" : ""; in rc_print_pair_instruction()
441 const char* neg = inst->Alpha.Arg[arg].Negate ? "-" : ""; in rc_print_pair_instruction()
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| D | radeon_program_alu.c | 152 newreg.Negate = RC_MASK_NONE; in absolute()
159 newreg.Negate = newreg.Negate ^ RC_MASK_XYZW; in negate()
234 src.Negate = RC_MASK_NONE; in transform_ABS()
280 src0.Negate &= ~(RC_MASK_Z | RC_MASK_W); in transform_DP2()
283 src1.Negate &= ~(RC_MASK_Z | RC_MASK_W); in transform_DP2()
294 src0.Negate &= ~RC_MASK_W; in transform_DPH()
701 inst->U.I.SrcReg[1].Negate ^= RC_MASK_XYZW; in transform_r300_vertex_ABS()
746 src0.Negate &= ~RC_MASK_W; in transform_r300_vertex_DP3()
749 src1.Negate &= ~RC_MASK_W; in transform_r300_vertex_DP3()
839 inst->U.I.SrcReg[0].Negate ^= RC_MASK_XYZW; in transform_r300_vertex_SGT()
[all …]
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| D | radeon_inline_literals.c | 162 src_reg->Negate = src_reg->Negate ^ negate_mask; in rc_inline_literals()
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| D | radeon_program_tex.c | 230 inst_add->U.I.SrcReg[1].Negate = inst_add->U.I.SrcReg[1].Negate ^ RC_MASK_XYZW; in radeonTransformTEX()
232 inst_add->U.I.SrcReg[0].Negate = inst_add->U.I.SrcReg[0].Negate ^ RC_MASK_XYZW; in radeonTransformTEX()
361 inst_mad->U.I.SrcReg[2].Negate = RC_MASK_XYZ; in radeonTransformTEX()
374 inst_add->U.I.SrcReg[1].Negate = RC_MASK_XYZ; in radeonTransformTEX()
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| /external/deqp-deps/glslang/Test/baseResults/ |
| D | hlsl.isfinite.frag.out | 11 0:8 Negate conditional ( temp bool)
19 0:8 Negate conditional ( temp bool)
22 0:8 Negate conditional ( temp bool)
36 0:13 Negate conditional ( temp bool)
39 0:13 Negate conditional ( temp bool)
50 0:14 Negate conditional ( temp 2-component vector of bool)
53 0:14 Negate conditional ( temp 2-component vector of bool)
64 0:15 Negate conditional ( temp 3-component vector of bool)
67 0:15 Negate conditional ( temp 3-component vector of bool)
99 0:8 Negate conditional ( temp bool)
[all …]
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| D | hlsl.logical.unary.frag.out | 8 0:13 Negate conditional ( temp bool)
14 0:14 Negate conditional ( temp 4-component vector of bool)
20 0:16 Negate conditional ( temp bool)
26 0:17 Negate conditional ( temp 4-component vector of bool)
50 0:21 Negate conditional ( temp bool)
59 0:22 Negate conditional ( temp bool)
102 0:13 Negate conditional ( temp bool)
108 0:14 Negate conditional ( temp 4-component vector of bool)
114 0:16 Negate conditional ( temp bool)
120 0:17 Negate conditional ( temp 4-component vector of bool)
[all …]
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| D | hlsl.frag.out | 46 0:9 Negate value (temp 4-component vector of float)
47 0:9 Negate value (temp 4-component vector of float)
111 0:9 Negate value (temp 4-component vector of float)
112 0:9 Negate value (temp 4-component vector of float)
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| D | vulkan.ast.vert.out | 55 0:26 Negate value ( temp highp float)
58 0:27 Negate conditional ( specialization-constant const bool)
61 0:28 Negate value ( specialization-constant const highp int)
186 0:26 Negate value ( temp highp float)
189 0:27 Negate conditional ( specialization-constant const bool)
192 0:28 Negate value ( specialization-constant const highp int)
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| /external/tensorflow/tensorflow/lite/kernels/ |
| D | neg.cc | 39 void Negate(const T* in_data, int num_elements, T* out_data) { in Negate() function
52 Negate(input->data.i64, num_elements, output->data.i64); in Eval()
55 Negate(input->data.i32, num_elements, output->data.i32); in Eval()
58 Negate(input->data.f, num_elements, output->data.f); in Eval()
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| /external/virglrenderer/src/gallium/auxiliary/tgsi/ |
| D | tgsi_util.c | 116 if( reg->Register.Negate ) { in tgsi_util_get_full_src_register_sign_mode()
124 if( reg->Register.Negate ) { in tgsi_util_get_full_src_register_sign_mode()
143 reg->Register.Negate = 0; in tgsi_util_set_full_src_register_sign_mode()
149 reg->Register.Negate = 1; in tgsi_util_set_full_src_register_sign_mode()
153 reg->Register.Negate = 1; in tgsi_util_set_full_src_register_sign_mode()
158 reg->Register.Negate = 0; in tgsi_util_set_full_src_register_sign_mode()
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| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| D | tgsi_util.c | 116 if (reg->Register.Negate) { in tgsi_util_get_full_src_register_sign_mode()
124 if (reg->Register.Negate) { in tgsi_util_get_full_src_register_sign_mode()
142 reg->Register.Negate = 0; in tgsi_util_set_full_src_register_sign_mode()
148 reg->Register.Negate = 1; in tgsi_util_set_full_src_register_sign_mode()
152 reg->Register.Negate = 1; in tgsi_util_set_full_src_register_sign_mode()
157 reg->Register.Negate = 0; in tgsi_util_set_full_src_register_sign_mode()
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| D | tgsi_lowering.c | 297 new_inst.Src[2].Register.Negate = !new_inst.Src[2].Register.Negate; in transform_lrp()
309 new_inst.Src[2].Register.Negate = true; in transform_lrp()
353 new_inst.Src[1].Register.Negate = 1; in transform_frc()
469 new_inst.Src[1].Register.Negate = true; in transform_lit()
507 new_inst.Src[0].Register.Negate = true; in transform_lit()
584 new_inst.Src[1].Register.Negate = 1; in transform_exp()
618 new_inst.Src[1].Register.Negate = 1; in transform_exp()
719 new_inst.Src[1].Register.Negate = 1; in transform_log()
923 new_inst.Src[0].Register.Negate = !new_inst.Src[0].Register.Negate; in transform_flr_ceil()
935 new_inst.Src[1].Register.Negate = 1; in transform_flr_ceil()
[all …]
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| /external/mesa3d/src/mesa/program/ |
| D | prog_opt_constant_fold.c | 85 && (a->Negate == b->Negate) in src_regs_are_same()
101 if (r->Negate & 0x01) { in get_value()
105 if (r->Negate & 0x02) { in get_value()
109 if (r->Negate & 0x04) { in get_value()
113 if (r->Negate & 0x08) { in get_value()
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| /external/mesa3d/src/mesa/drivers/dri/r200/ |
| D | r200_vertprog.c | 287 src->Negate) | (src->RelAddr << 4); in t_src()
299 src->Negate ? VSF_FLAG_ALL : VSF_FLAG_NONE) | (src->RelAddr << 4); in t_src_scalar()
704 src[0].Negate) | (src[0].RelAddr << 4); in r200_translate_vertex_program()
716 src[0].Negate ? VSF_FLAG_ALL : VSF_FLAG_NONE) | (src[0].RelAddr << 4); in r200_translate_vertex_program()
721 src[1].Negate ? VSF_FLAG_ALL : VSF_FLAG_NONE) | (src[1].RelAddr << 4); in r200_translate_vertex_program()
770 src[1].Negate) | (src[1].RelAddr << 4); in r200_translate_vertex_program()
774 src[1].Negate) | (src[1].RelAddr << 4); in r200_translate_vertex_program()
796 src[0].Negate) | (src[0].RelAddr << 4); in r200_translate_vertex_program()
804 src[1].Negate) | (src[1].RelAddr << 4); in r200_translate_vertex_program()
819 src[0].Negate) | (src[0].RelAddr << 4); in r200_translate_vertex_program()
[all …]
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| /external/mesa3d/src/gallium/drivers/r300/compiler/tests/ |
| D | rc_test_helpers.c | 116 struct match_info Negate; member
152 tokens.Negate.String = src_str + matches[1].rm_so; in init_rc_normal_src()
153 tokens.Negate.Length = match_length(matches, 1); in init_rc_normal_src()
164 if (tokens.Negate.Length > 0) { in init_rc_normal_src()
165 src_reg->Negate = RC_MASK_XYZW; in init_rc_normal_src()
205 src_reg->Negate |= (1 << i); in init_rc_normal_src()
242 src_reg->Negate, src_reg->Abs); in init_rc_normal_src()
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| /external/clang/lib/Analysis/ |
| D | ThreadSafety.cpp | 945 bool &Negate);
1330 bool &Negate) { in getTrylockCallExpr() argument
1338 return getTrylockCallExpr(PE->getSubExpr(), C, Negate); in getTrylockCallExpr()
1341 return getTrylockCallExpr(CE->getSubExpr(), C, Negate); in getTrylockCallExpr()
1344 return getTrylockCallExpr(EWC->getSubExpr(), C, Negate); in getTrylockCallExpr()
1348 return getTrylockCallExpr(E, C, Negate); in getTrylockCallExpr()
1352 Negate = !Negate; in getTrylockCallExpr()
1353 return getTrylockCallExpr(UOP->getSubExpr(), C, Negate); in getTrylockCallExpr()
1360 Negate = !Negate; in getTrylockCallExpr()
1364 if (!TCond) Negate = !Negate; in getTrylockCallExpr()
[all …]
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| /external/mesa3d/src/gallium/drivers/i915/ |
| D | i915_fpc_optimize.c | 69 d1->Register.Negate == d2->Register.Negate); in same_src_reg()
228 o->Negate = i->Negate; in copy_src_reg()
552 current.FullInstruction.Src[0].Register.Negate == 0 && in i915_fpc_useless_mov()
582 next->FullInstruction.Src[0].Register.Negate == 0 && in i915_fpc_optimize_useless_mov_after_inst()
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| /external/tensorflow/tensorflow/compiler/xla/service/ |
| D | defuser_test.cc | 101 EXPECT_THAT(computation->root_instruction(), op::Negate(op::Fusion())); in TEST_F()
108 op::Negate(op::Add(op::Parameter(), op::Parameter()))); in TEST_F()
216 EXPECT_THAT(computation->root_instruction(), op::Negate(op::Add())); in TEST_F()
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