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Searched refs:Neon32 (Results 1 – 6 of 6) sorted by relevance

/external/v8/src/arm/
Dsimulator-arm.cc3393 NeonSize size = Neon32; in DecodeTypeVFP()
3420 case Neon32: { in DecodeTypeVFP()
4268 case Neon32: in DecodeSpecialCondition()
4321 case Neon32: in DecodeSpecialCondition()
4344 case Neon32: in DecodeSpecialCondition()
4364 case Neon32: in DecodeSpecialCondition()
4385 case Neon32: in DecodeSpecialCondition()
4401 case Neon32: in DecodeSpecialCondition()
4422 case Neon32: in DecodeSpecialCondition()
4445 case Neon32: in DecodeSpecialCondition()
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Dconstants-arm.h308 enum NeonSize { Neon8 = 0x0, Neon16 = 0x1, Neon32 = 0x2, Neon64 = 0x3 }; enumerator
Dmacro-assembler-arm.cc907 vdup(Neon32, scratch, src_d_reg, src_offset); in VmovExtended()
914 vdup(Neon32, dst_d_reg, src_d_reg, 0); in VmovExtended()
920 vdup(Neon32, dst_d_reg, src_d_reg, 1); in VmovExtended()
Dassembler-arm.cc3993 case Neon32: in vdup()
4119 DCHECK_EQ(Neon32, size); in EncodeNeonUnaryOp()
4126 DCHECK_EQ(Neon32, size); in EncodeNeonUnaryOp()
4168 emit(EncodeNeonUnaryOp(VABSF, NEON_Q, Neon32, dst.code(), src.code())); in vabs()
4182 emit(EncodeNeonUnaryOp(VNEGF, NEON_Q, Neon32, dst.code(), src.code())); in vneg()
4826 if (size == Neon32) { // vzip.32 Dd, Dm is a pseudo-op for vtrn.32 Dd, Dm. in vzip()
4844 if (size == Neon32) { // vuzp.32 Dd, Dm is a pseudo-op for vtrn.32 Dd, Dm. in vuzp()
/external/v8/src/compiler/arm/
Dcode-generator-arm.cc1777 __ vdup(Neon32, i.OutputSimd128Register(), in AssembleArchInstruction()
1880 __ vdup(Neon32, i.OutputSimd128Register(), i.InputRegister(0)); in AssembleArchInstruction()
1908 __ vneg(Neon32, i.OutputSimd128Register(), i.InputSimd128Register(0)); in AssembleArchInstruction()
1922 __ vadd(Neon32, i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction()
1927 ASSEMBLE_NEON_PAIRWISE_OP(vpadd, Neon32); in AssembleArchInstruction()
1930 __ vsub(Neon32, i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction()
1935 __ vmul(Neon32, i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction()
1950 __ vceq(Neon32, i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction()
1956 __ vceq(Neon32, dst, i.InputSimd128Register(0), in AssembleArchInstruction()
2332 __ vtrn(Neon32, dst.low(), dst.high()); // dst = [0, 4, 1, 5] in AssembleArchInstruction()
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Dinstruction-selector-arm.cc2719 g.UseImmediate(Neon32), g.UseImmediate(index % 4)); in VisitS8x16Shuffle()